back.pysim: fix handling of process termination.

diff --git a/examples/ctrl.py b/examples/ctrl.py
index 17a9e9481a2c6d90ddc2dc4de24028a6a91a34ca..4d33e2684220f2afc2baa34b70301875b288be11 100644 (file)
--- a/examples/ctrl.py
+++ b/examples/ctrl.py
@@ -1,5 +1,5 @@
 from nmigen.fhdl import *
-from nmigen.back import rtlil, verilog
+from nmigen.back import rtlil, verilog, pysim
 
 
 class ClockDivisor:
@@ -17,5 +17,16 @@ class ClockDivisor:
 
 ctr  = ClockDivisor(factor=16)
 frag = ctr.get_fragment(platform=None)
+
 # print(rtlil.convert(frag, ports=[ctr.o, ctr.ce]))
 print(verilog.convert(frag, ports=[ctr.o, ctr.ce]))
+
+sim = pysim.Simulator(frag, vcd_file=open("ctrl.vcd", "w"))
+sim.add_clock("sync", 1e-6)
+def sim_proc():
+    yield pysim.Delay(15.25e-6)
+    yield ctr.ce.eq(Const(1))
+    yield pysim.Delay(15e-6)
+    yield ctr.ce.eq(Const(0))
+sim.add_process(sim_proc())
+with sim: sim.run_until(100e-6, run_passive=True)

diff --git a/nmigen/back/pysim.py b/nmigen/back/pysim.py
index 2afffabbdab884ac671ba7ba9677dce2a18f1555..fc298cfc04220a27bfbeafa39f0cd0ce49cc5105 100644 (file)
--- a/nmigen/back/pysim.py
+++ b/nmigen/back/pysim.py
@@ -320,8 +320,7 @@ class Simulator:
             stmt = proc.send(None)
         except StopIteration:
             self._processes.remove(proc)
-            self._passive.remove(proc)
-            self._suspended.remove(proc)
+            self._passive.discard(proc)
             return
 
         if isinstance(stmt, Delay):