winsys/amdgpu: addrlib - port a Fiji bug fix

Fiji: Fixed tiled resource failures

Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
v2: fix a compile failure (typo) - Marek

diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
index 7393953c120ae394a62787f223652bc8f2159a3e..570216241d1eba745e3fd637d50610681ee9aeb7 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
@@ -894,6 +894,49 @@ BOOL_32 CIAddrLib::HwlOverrideTileMode(
     return bOverrided;
 }
 
+/**
+***************************************************************************************************
+*   CiAddrLib::GetPrtSwitchP4Threshold
+*
+*   @brief
+*       Return the threshold of switching to P4_* instead of P16_* for PRT resources
+***************************************************************************************************
+*/
+UINT_32 CIAddrLib::GetPrtSwitchP4Threshold() const
+{
+    UINT_32 threshold;
+
+    switch (m_pipes)
+    {
+        case 8:
+            threshold = 32;
+            break;
+        case 16:
+            if (m_settings.isFiji)
+            {
+                threshold = 16;
+            }
+            else if (m_settings.isHawaii)
+            {
+                threshold = 8;
+            }
+            else
+            {
+                ///@todo add for possible new ASICs.
+                ADDR_ASSERT_ALWAYS();
+                threshold = 16;
+            }
+            break;
+        default:
+            ///@todo add for possible new ASICs.
+            ADDR_ASSERT_ALWAYS();
+            threshold = 32;
+            break;
+    }
+
+    return threshold;
+}
+
 /**
 ***************************************************************************************************
 *   CIAddrLib::HwlSetupTileInfo
@@ -1123,7 +1166,7 @@ VOID CIAddrLib::HwlSetupTileInfo(
             {
                 UINT_32 bytesXSamples = bpp * numSamples / 8;
                 UINT_32 bytesXThickness = bpp * thickness / 8;
-                UINT_32 switchP4Threshold = (m_pipes == 16) ? 8 : 32;
+                UINT_32 switchP4Threshold = GetPrtSwitchP4Threshold();
 
                 if ((bytesXSamples > switchP4Threshold) || (bytesXThickness > switchP4Threshold))
                 {

diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
index 451508619f96757d2ce645b299bfa4d32562801d..4cbe9706baac012033ff550813e22ea1ee63e736 100644 (file)
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
@@ -167,6 +167,8 @@ private:
     VOID ReadGbMacroTileCfg(
         UINT_32 regValue, ADDR_TILEINFO* pCfg) const;
 
+    UINT_32 GetPrtSwitchP4Threshold() const;
+
     BOOL_32 InitTileSettingTable(
         const UINT_32 *pSetting, UINT_32 noOfEntries);