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whoops forgot elif in SVP64Asm translation, detection of ffmadds overwritten
authorLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 10 Jul 2021 16:24:10 +0000 (17:24 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sat, 10 Jul 2021 16:24:10 +0000 (17:24 +0100)
src/openpower/sv/trans/svp64.py patch | blob | history

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index 05f976324641d918e38f8d91d57e0df475f2ec2a..6fc57705d9ac6061c27fef69a45971a38b071214 100644 (file)
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -818,7 +818,7 @@ class SVP64Asm:
                 opcode |= 1  # Rc, bit 31.
             yield ".long 0x%x" % opcode
         # argh, sv.ffadds etc. need to be done manually
-        if v30b_op == 'ffadds':
+        elif v30b_op == 'ffadds':
             opcode = 59 << (32-6)    # bits 0..6 (MSB0)
             opcode |= int(v30b_newfields[0]) << (32-11) # FRT
             opcode |= int(v30b_newfields[1]) << (32-16) # FRA