AArch64 Support abs standard pattern for DI mode

From-SVN: r200596

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 5f41e369e1fe9884da120afd4d63b932153c1aba..d1e6ea3b3aee0fda66f19fb9f2d3e74280cb315b 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+2013-07-02  Ian Bolton  <ian.bolton@arm.com>
+
+       * config/aarch64/aarch64-simd.md (absdi2): Support abs for
+       DI mode.
+
 2013-07-02  Ian Bolton  <ian.bolton@arm.com>
 
        * config/aarch64/aarch64.md (*extr_insv_reg<mode>): New pattern.

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index d06a202e9210a2e2f9d7db3d38e7f6dd9cdea31c..68336db0ed5062f3a41675b3bde484cc36ba1ad9 100644 (file)
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -2003,6 +2003,38 @@
    (set_attr "mode" "SI")]
 )
 
+(define_insn_and_split "absdi2"
+  [(set (match_operand:DI 0 "register_operand" "=r,w")
+       (abs:DI (match_operand:DI 1 "register_operand" "r,w")))
+   (clobber (match_scratch:DI 2 "=&r,X"))]
+  ""
+  "@
+   #
+   abs\\t%d0, %d1"
+  "reload_completed
+   && GP_REGNUM_P (REGNO (operands[0]))
+   && GP_REGNUM_P (REGNO (operands[1]))"
+  [(const_int 0)]
+  {
+    emit_insn (gen_rtx_SET (VOIDmode, operands[2],
+                           gen_rtx_XOR (DImode,
+                                        gen_rtx_ASHIFTRT (DImode,
+                                                          operands[1],
+                                                          GEN_INT (63)),
+                                        operands[1])));
+    emit_insn (gen_rtx_SET (VOIDmode,
+                           operands[0],
+                           gen_rtx_MINUS (DImode,
+                                          operands[2],
+                                          gen_rtx_ASHIFTRT (DImode,
+                                                            operands[1],
+                                                            GEN_INT (63)))));
+    DONE;
+  }
+  [(set_attr "v8type" "alu")
+   (set_attr "mode" "DI")]
+)
+
 (define_insn "neg<mode>2"
   [(set (match_operand:GPI 0 "register_operand" "=r")
        (neg:GPI (match_operand:GPI 1 "register_operand" "r")))]

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 7357b3c386c87cc4929cf8ad1c341745ad20602d..52cf0bc63c00e8c4f0b19e38974977ff5a0a4875 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2013-07-02  Ian Bolton  <ian.bolton@arm.com>
+
+       * gcc.target/aarch64/abs_1.c: New test.
+
 2013-07-02  Ian Bolton  <ian.bolton@arm.com>
 
        * gcc.target/aarch64/bfxil_1.c: New test.

diff --git a/gcc/testsuite/gcc.target/aarch64/abs_1.c b/gcc/testsuite/gcc.target/aarch64/abs_1.c
new file mode 100644 (file)
index 0000000..938bc84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/abs_1.c
@@ -0,0 +1,53 @@
+/* { dg-do run } */
+/* { dg-options "-O2 -fno-inline --save-temps" } */
+
+extern long long llabs (long long);
+extern void abort (void);
+
+long long
+abs64 (long long a)
+{
+  /* { dg-final { scan-assembler "eor\t" } } */
+  /* { dg-final { scan-assembler "sub\t" } } */
+  return llabs (a);
+}
+
+long long
+abs64_in_dreg (long long a)
+{
+  /* { dg-final { scan-assembler "abs\td\[0-9\]+, d\[0-9\]+" } } */
+  register long long x asm ("d8") = a;
+  register long long y asm ("d9");
+  asm volatile ("" : : "w" (x));
+  y = llabs (x);
+  asm volatile ("" : : "w" (y));
+  return y;
+}
+
+int
+main (void)
+{
+  volatile long long ll0 = 0LL, ll1 = 1LL, llm1 = -1LL;
+
+  if (abs64 (ll0) != 0LL)
+    abort ();
+
+  if (abs64 (ll1) != 1LL)
+    abort ();
+
+  if (abs64 (llm1) != 1LL)
+    abort ();
+
+  if (abs64_in_dreg (ll0) != 0LL)
+    abort ();
+
+  if (abs64_in_dreg (ll1) != 1LL)
+    abort ();
+
+  if (abs64_in_dreg (llm1) != 1LL)
+    abort ();
+
+  return 0;
+}
+
+/* { dg-final { cleanup-saved-temps } } */