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added lwzsux instruction
authorShriya Sharma <shriya@redsemiconductor.com>
Thu, 19 Oct 2023 10:25:04 +0000 (11:25 +0100)
committerLuke Kenneth Casson Leighton <lkcl@lkcl.net>
Sun, 29 Oct 2023 08:54:37 +0000 (08:54 +0000)
openpower/isa/fixedloadshift.mdwn patch | blob | history

diff --git a/openpower/isa/fixedloadshift.mdwn b/openpower/isa/fixedloadshift.mdwn
index 0d43c5c128fe96fb48673e09564720e84b8ff986..9fdc716f057bf4d1acdc22bbe895ce67539e134a 100644 (file)
--- a/openpower/isa/fixedloadshift.mdwn
+++ b/openpower/isa/fixedloadshift.mdwn
@@ -138,15 +138,15 @@ Special Registers Altered:
 
     None
 
-# Load Word and Zero with Update Indexed
+# Load Word and Zero Shifted with Update Indexed
 
 X-Form
 
-* lwzux RT,RA,RB
+* lwzsux RT,RA,RB,sm
 
 Pseudo-code:
 
-    EA <- (RA) + (RB)
+    EA <- (RA) + (RB) << (sm+1)
     RT <- [0] * 32 || MEM(EA, 4)
     RA <- EA