observation motivation on ls002, even FPR=0 needs FLD

diff --git a/openpower/sv/rfc/ls002.mdwn b/openpower/sv/rfc/ls002.mdwn
index 2971f9dbec7cef15cdbf4e746d03815921198d57..096da9a3a5d3dfd481df99156851f75740278922 100644 (file)
--- a/openpower/sv/rfc/ls002.mdwn
+++ b/openpower/sv/rfc/ls002.mdwn
@@ -57,7 +57,7 @@
 Similar to `lxvkq` but extended to a full BF16 with one
 32-bit instruction and a full FP32 in two 32-bit instructions
 these instructions always save a Data Load and associated L1
-and TLB lookup.
+and TLB lookup. Even clearing an FPR to zero presently requires Load.
 
 **Notes and Observations**: