imported patch squash_from_next_stage

diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index dbee7f46c9688caa2676d6692f6a8361dae8d060..03c44ea86aa5fbf6940304e6b96144ffbe9b3a8c 100644 (file)
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -1130,6 +1130,7 @@ InOrderCPU::getPipeStage(int stage_num)
     return pipelineStage[stage_num];
 }
 
+
 RegIndex
 InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
 {
@@ -1455,29 +1456,31 @@ InOrderCPU::removeInstsUntil(const InstSeqNum &seq_num, ThreadID tid)
 
 
 inline void
-InOrderCPU::squashInstIt(const ListIt &instIt, ThreadID tid)
+InOrderCPU::squashInstIt(const ListIt inst_it, ThreadID tid)
 {
-    if ((*instIt)->threadNumber == tid) {
+    DynInstPtr inst = (*inst_it);
+    if (inst->threadNumber == tid) {
         DPRINTF(InOrderCPU, "Squashing instruction, "
                 "[tid:%i] [sn:%lli] PC %s\n",
-                (*instIt)->threadNumber,
-                (*instIt)->seqNum,
-                (*instIt)->pcState());
+                inst->threadNumber,
+                inst->seqNum,
+                inst->pcState());
 
-        (*instIt)->setSquashed();
+        inst->setSquashed();
+        archRegDepMap[tid].remove(inst);
 
-        if (!(*instIt)->isRemoveList()) {            
+        if (!inst->isRemoveList()) {
             DPRINTF(InOrderCPU, "Pushing instruction [tid:%i] PC %s "
                     "[sn:%lli] to remove list\n",
-                    (*instIt)->threadNumber, (*instIt)->pcState(),
-                    (*instIt)->seqNum);
-            (*instIt)->setRemoveList();        
-            removeList.push(instIt);
+                    inst->threadNumber, inst->pcState(),
+                    inst->seqNum);
+            inst->setRemoveList();
+            removeList.push(inst_it);
         } else {
             DPRINTF(InOrderCPU, "Ignoring instruction removal for [tid:%i]"
                     " PC %s [sn:%lli], already on remove list\n",
-                    (*instIt)->threadNumber, (*instIt)->pcState(),
-                    (*instIt)->seqNum);
+                    inst->threadNumber, inst->pcState(),
+                    inst->seqNum);
         }
     
     }
@@ -1499,7 +1502,7 @@ InOrderCPU::cleanUpRemovedInsts()
         ThreadID tid = inst->threadNumber;
 
         // Remove From Register Dependency Map, If Necessary
-        archRegDepMap[tid].remove(inst);
+        // archRegDepMap[tid].remove(inst);
 
         // Clear if Non-Speculative
         if (inst->staticInst &&

diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index 051a790dbedfdabf8e710ad35691ed25bf8b0b41..c8ac33a89240e73f65b8399fd352e104bf0d2546 100644 (file)
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -547,6 +547,16 @@ class InOrderCPU : public BaseCPU
 
     void setFloatRegBits(RegIndex reg_idx, FloatRegBits val,  ThreadID tid);
 
+    RegType inline getRegType(RegIndex reg_idx)
+    {
+        if (reg_idx < TheISA::FP_Base_DepTag)
+            return IntType;
+        else if (reg_idx < TheISA::Ctrl_Base_DepTag)
+            return FloatType;
+        else
+            return MiscType;
+    }
+
     RegIndex flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid);
 
     /** Reads a miscellaneous register. */
@@ -617,7 +627,7 @@ class InOrderCPU : public BaseCPU
     void removeInstsUntil(const InstSeqNum &seq_num,ThreadID tid);
 
     /** Removes the instruction pointed to by the iterator. */
-    inline void squashInstIt(const ListIt &instIt, ThreadID tid);
+    inline void squashInstIt(const ListIt inst_it, ThreadID tid);
 
     /** Cleans up all instructions on the instruction remove list. */
     void cleanUpRemovedInsts();

diff --git a/src/cpu/inorder/pipeline_stage.cc b/src/cpu/inorder/pipeline_stage.cc
index d37779ce8eb5ed5237c5c850210ac6103cff2b2e..2e9ca64e3743fc5f3b6a775d1207213087f70bdc 100644 (file)
--- a/src/cpu/inorder/pipeline_stage.cc
+++ b/src/cpu/inorder/pipeline_stage.cc
@@ -351,9 +351,11 @@ PipelineStage::setupSquash(DynInstPtr inst, ThreadID tid)
                 inst->seqNum, cpu->squashSeqNum[tid]);
     } else {
         InstSeqNum squash_seq_num = inst->squashSeqNum;
+        unsigned squash_stage = (nextStageValid) ? stageNum + 1
+            : stageNum;
 
-        toPrevStages->stageInfo[stageNum][tid].squash = true;
-        toPrevStages->stageInfo[stageNum][tid].doneSeqNum =
+        toPrevStages->stageInfo[squash_stage][tid].squash = true;
+        toPrevStages->stageInfo[squash_stage][tid].doneSeqNum =
             squash_seq_num;
 
         DPRINTF(InOrderStage, "[tid:%i]: Squashing after [sn:%i], "

diff --git a/src/cpu/inorder/reg_dep_map.cc b/src/cpu/inorder/reg_dep_map.cc
index b95450f9d5fd522bfe7d7d9a60cc417deec95d56..9898de43d9b475f66fe8d4e22a71fac5e6235af5 100644 (file)
--- a/src/cpu/inorder/reg_dep_map.cc
+++ b/src/cpu/inorder/reg_dep_map.cc
@@ -89,7 +89,7 @@ RegDepMap::insert(DynInstPtr inst)
     DPRINTF(RegDepMap, "Setting Output Dependencies for [sn:%i] "
             ", %s (dest. regs = %i).\n",
             inst->seqNum,
-            inst->staticInst->getName(),
+            inst->instName(),
             dest_regs);
 
     for (int i = 0; i < dest_regs; i++) {
@@ -98,6 +98,10 @@ RegDepMap::insert(DynInstPtr inst)
         TheISA::RegIndex flat_idx = cpu->flattenRegIdx(raw_idx,
                                                        reg_type,
                                                        inst->threadNumber);
+
+        DPRINTF(RegDepMap, "[sn:%i] #%i flattened %i to %i.\n",
+                inst->seqNum, i, raw_idx, flat_idx);
+
         inst->flattenDestReg(i, flat_idx);
         insert(reg_type, flat_idx, inst);
     }
@@ -120,32 +124,40 @@ void
 RegDepMap::remove(DynInstPtr inst)
 {
     if (inst->isRegDepEntry()) {
-        DPRINTF(RegDepMap, "Removing [sn:%i]'s entries from reg. dep. map.\n",
-                inst->seqNum);
-
         int dest_regs = inst->numDestRegs();
-        for (int i = 0; i < dest_regs; i++)
-            remove(inst->destRegIdx(i), inst);
+
+        DPRINTF(RegDepMap, "Removing [sn:%i]'s entries from reg. dep. map. for "
+                ", %s (dest. regs = %i).\n",
+                inst->seqNum,
+                inst->instName(),
+                dest_regs);
+
+
+        for (int i = 0; i < dest_regs; i++) {
+            InOrderCPU::RegType reg_type = cpu->getRegType(inst->destRegIdx(i));
+            remove(reg_type, inst->flattenedDestRegIdx(i), inst);
+        }
     }
 }
 
 void
-RegDepMap::remove(RegIndex idx, DynInstPtr inst)
+RegDepMap::remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
 {
-    InOrderCPU::RegType reg_type;
-    TheISA::RegIndex flat_idx = cpu->flattenRegIdx(idx, reg_type,
-                                                   inst->threadNumber);
+    std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
+    std::list<DynInstPtr>::iterator list_end = regMap[reg_type][idx].end();
 
-    std::list<DynInstPtr>::iterator list_it = regMap[reg_type][flat_idx].begin();
-    std::list<DynInstPtr>::iterator list_end = regMap[reg_type][flat_idx].end();
 
     while (list_it != list_end) {
         if((*list_it) == inst) {
-            regMap[reg_type][flat_idx].erase(list_it);
-            break;
+            DPRINTF(RegDepMap, "Removing [sn:%i] from %s dep. list for "
+                    "reg. idx %i.\n", inst->seqNum, mapNames[reg_type],
+                    idx);
+            regMap[reg_type][idx].erase(list_it);
+            return;
         }
         list_it++;
     }
+    panic("[sn:%i] Did not find entry for %i ", inst->seqNum, idx);
 }
 
 void
@@ -153,7 +165,7 @@ RegDepMap::removeFront(uint8_t reg_type, RegIndex idx, DynInstPtr inst)
 {
    std::list<DynInstPtr>::iterator list_it = regMap[reg_type][idx].begin();
 
-   DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx"
+   DPRINTF(RegDepMap, "[tid:%u]: Removing dependency entry on reg. idx "
            "%i for [sn:%i].\n", inst->readTid(), idx, inst->seqNum);
 
    assert(list_it != regMap[reg_type][idx].end());

diff --git a/src/cpu/inorder/reg_dep_map.hh b/src/cpu/inorder/reg_dep_map.hh
index 03eb6bd65d95a98fbc49c873460c083dfd108e65..fa69e22342166f7173685fccd52b36c96865226c 100644 (file)
--- a/src/cpu/inorder/reg_dep_map.hh
+++ b/src/cpu/inorder/reg_dep_map.hh
@@ -98,10 +98,8 @@ class RegDepMap
      */
     void insert(uint8_t reg_type, RegIndex idx, DynInstPtr inst);
 
-    /** Remove a specific instruction and dest. register index from map
-     *  This must be called w/the unflattened registered index
-     */
-    void remove(RegIndex idx, DynInstPtr inst);
+    /** Remove a specific instruction and dest. register index from map */
+    void remove(uint8_t reg_type, RegIndex idx, DynInstPtr inst);
 
     typedef std::vector<std::list<DynInstPtr> > DepMap;
     std::vector<DepMap> regMap;

diff --git a/src/cpu/inorder/resources/decode_unit.cc b/src/cpu/inorder/resources/decode_unit.cc
index 43f8478188adc80ba2ce6f78c14822377891c2d8..0ab9d96c7225053a1d1283d124982076a5f70b23 100644 (file)
--- a/src/cpu/inorder/resources/decode_unit.cc
+++ b/src/cpu/inorder/resources/decode_unit.cc
@@ -66,11 +66,8 @@ DecodeUnit::execute(int slot_num)
 
             if (inst->backSked != NULL) {
                 DPRINTF(InOrderDecode,
-                    "[tid:%i]: %s Setting Destination Register(s) for [sn:%i].\n",
+                    "[tid:%i]: Back End Schedule created for %s  [sn:%i].\n",
                         tid, inst->instName(), inst->seqNum);
-
-                //inst->printSked();
-
                 decode_req->done();
             } else {
                 DPRINTF(Resource,