include/opcode/

	* mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
	(MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
	(MIPS16_INSN_COND_BRANCH): Delete.

opcodes/
	* mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
	(WR_SP): Replace with...
	(MOD_SP): ...this.
	(mips16_opcodes): Update accordingly.
	* mips-dis.c (print_insn_mips16): Likewise.

gas/
	* config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
	flags for MIPS16 and non-MIPS16 instructions.
	(gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
	(gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
	(gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
	(can_swap_branch_p, get_append_method): Use the same flags for MIPS16
	and non-MIPS16 instructions.  Fix formatting.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index e1cab9afeb66fb89be4d2ff9dd6e1ea2820451f9..1a838dd4719dd745df595dc1761b2711f3d7a27b 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * config/tc-mips.c (compact_branch_p, uncond_branch_p): Use the same
+       flags for MIPS16 and non-MIPS16 instructions.
+       (gpr_mod_mask): Move the INSN2_MOD_SP case outside the micromips block.
+       (gpr_read_mask): Use INSN2_READ_GPR_31 for MIPS16 instructions too.
+       (gpr_write_mask): Remove MIPS16_INSN_WRITE_SP handling.
+       (can_swap_branch_p, get_append_method): Use the same flags for MIPS16
+       and non-MIPS16 instructions.  Fix formatting.
+
 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * config/tc-mips.c (reg_needs_delay): Move later in file.

diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index 68241a0024d8435da3bc90fb856074d4fb7d9523..91e6a970b0614869654a1bd07df376a380cb7745 100644 (file)
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -3547,12 +3547,8 @@ delayed_branch_p (const struct mips_cl_insn *ip)
 static inline bfd_boolean
 compact_branch_p (const struct mips_cl_insn *ip)
 {
-  if (mips_opts.mips16)
-    return (ip->insn_mo->pinfo & (MIPS16_INSN_UNCOND_BRANCH
-                                 | MIPS16_INSN_COND_BRANCH)) != 0;
-  else
-    return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
-                                  | INSN2_COND_BRANCH)) != 0;
+  return (ip->insn_mo->pinfo2 & (INSN2_UNCOND_BRANCH
+                                | INSN2_COND_BRANCH)) != 0;
 }
 
 /* Return true if IP is an unconditional branch or jump.  */
@@ -3561,9 +3557,7 @@ static inline bfd_boolean
 uncond_branch_p (const struct mips_cl_insn *ip)
 {
   return ((ip->insn_mo->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
-         || (mips_opts.mips16
-             ? (ip->insn_mo->pinfo & MIPS16_INSN_UNCOND_BRANCH) != 0
-             : (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0));
+         || (ip->insn_mo->pinfo2 & INSN2_UNCOND_BRANCH) != 0);
 }
 
 /* Return true if IP is a branch-likely instruction.  */
@@ -3602,9 +3596,9 @@ gpr_mod_mask (const struct mips_cl_insn *ip)
        mask |= 1 << micromips_to_32_reg_d_map[EXTRACT_OPERAND (1, MD, *ip)];
       if (pinfo2 & INSN2_MOD_GPR_MF)
        mask |= 1 << micromips_to_32_reg_f_map[EXTRACT_OPERAND (1, MF, *ip)];
-      if (pinfo2 & INSN2_MOD_SP)
-       mask |= 1 << SP;
     }
+  if (pinfo2 & INSN2_MOD_SP)
+    mask |= 1 << SP;
   return mask;
 }
 
@@ -3629,8 +3623,6 @@ gpr_read_mask (const struct mips_cl_insn *ip)
        mask |= 1 << TREG;
       if (pinfo & MIPS16_INSN_READ_SP)
        mask |= 1 << SP;
-      if (pinfo & MIPS16_INSN_READ_31)
-       mask |= 1 << RA;
       if (pinfo & MIPS16_INSN_READ_Z)
        mask |= 1 << (mips16_to_32_reg_map
                      [MIPS16_EXTRACT_OPERAND (MOVE32Z, *ip)]);
@@ -3647,11 +3639,11 @@ gpr_read_mask (const struct mips_cl_insn *ip)
        mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RS, *ip);
       if (pinfo2 & INSN2_READ_GP)
        mask |= 1 << GP;
-      if (pinfo2 & INSN2_READ_GPR_31)
-       mask |= 1 << RA;
       if (pinfo2 & INSN2_READ_GPR_Z)
        mask |= 1 << EXTRACT_OPERAND (mips_opts.micromips, RZ, *ip);
     }
+  if (pinfo2 & INSN2_READ_GPR_31)
+    mask |= 1 << RA;
   if (mips_opts.micromips)
     {
       if (pinfo2 & INSN2_READ_GPR_MC)
@@ -3697,8 +3689,6 @@ gpr_write_mask (const struct mips_cl_insn *ip)
        mask |= 1 << mips16_to_32_reg_map[MIPS16_EXTRACT_OPERAND (RZ, *ip)];
       if (pinfo & MIPS16_INSN_WRITE_T)
        mask |= 1 << TREG;
-      if (pinfo & MIPS16_INSN_WRITE_SP)
-       mask |= 1 << SP;
       if (pinfo & MIPS16_INSN_WRITE_31)
        mask |= 1 << RA;
       if (pinfo & MIPS16_INSN_WRITE_GPR_Y)
@@ -5603,7 +5593,7 @@ fix_loongson2f (struct mips_cl_insn * ip)
 
 static bfd_boolean
 can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
-  bfd_reloc_code_real_type *reloc_type)
+                  bfd_reloc_code_real_type *reloc_type)
 {
   unsigned long pinfo, pinfo2, prev_pinfo, prev_pinfo2;
   unsigned int gpr_read, gpr_write, prev_gpr_read, prev_gpr_write;
@@ -5705,9 +5695,7 @@ can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
 
   /* If the previous instruction uses the PC, we can not swap.  */
   prev_pinfo2 = history[0].insn_mo->pinfo2;
-  if (mips_opts.mips16 && (prev_pinfo & MIPS16_INSN_READ_PC))
-    return FALSE;
-  if (mips_opts.micromips && (prev_pinfo2 & INSN2_READ_PC))
+  if (prev_pinfo2 & INSN2_READ_PC)
     return FALSE;
 
   /* If the previous instruction has an incorrect size for a fixed
@@ -5779,9 +5767,9 @@ can_swap_branch_p (struct mips_cl_insn *ip, expressionS *address_expr,
 
 static enum append_method
 get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
-  bfd_reloc_code_real_type *reloc_type)
+                  bfd_reloc_code_real_type *reloc_type)
 {
-  unsigned long pinfo;
+  unsigned long pinfo, pinfo2;
 
   /* The relaxed version of a macro sequence must be inherently
      hazard-free.  */
@@ -5800,9 +5788,11 @@ get_append_method (struct mips_cl_insn *ip, expressionS *address_expr,
        return APPEND_SWAP;
 
       pinfo = ip->insn_mo->pinfo;
+      pinfo2 = ip->insn_mo->pinfo2;
       if (mips_opts.mips16
          && ISA_SUPPORTS_MIPS16E
-         && (pinfo & (MIPS16_INSN_READ_X | MIPS16_INSN_READ_31)))
+         && ((pinfo & MIPS16_INSN_READ_X) != 0
+             || (pinfo2 & INSN2_READ_GPR_31) != 0))
        return APPEND_ADD_COMPACT;
 
       return APPEND_ADD_WITH_NOP;

diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog
index 08e695b12beb426220a674d9713581379e6ac640..b3cbe9bdabd93be91f5e7de9bff66de606617187 100644 (file)
--- a/include/opcode/ChangeLog
+++ b/include/opcode/ChangeLog
@@ -1,3 +1,9 @@
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * mips.h (MIPS16_INSN_WRITE_SP, MIPS16_INSN_READ_31)
+       (MIPS16_INSN_READ_PC, MIPS16_INSN_UNCOND_BRANCH)
+       (MIPS16_INSN_COND_BRANCH): Delete.
+
 2013-07-24  Anna Tikhonova  <anna.tikhonova@intel.com>
            Kirill Yukhin  <kirill.yukhin@intel.com>
            Michael Zolotukhin  <michael.v.zolotukhin@intel.com>

diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index e2f72e0b019d11d98da2dd31f29f4f3f5d707c23..299c1ebf2b8054c7c2e243415d15257578f81c67 100644 (file)
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -1644,8 +1644,6 @@ extern int bfd_mips_num_opcodes;
 #define MIPS16_INSN_WRITE_Z                0x00000004
 /* Modifies the T ($24) register.  */
 #define MIPS16_INSN_WRITE_T                0x00000008
-/* Modifies the SP ($29) register.  */
-#define MIPS16_INSN_WRITE_SP               0x00000010
 /* Modifies the RA ($31) register.  */
 #define MIPS16_INSN_WRITE_31               0x00000020
 /* Modifies the general purpose register in MIPS16OP_*_REG32R.  */
@@ -1660,16 +1658,8 @@ extern int bfd_mips_num_opcodes;
 #define MIPS16_INSN_READ_T                 0x00000400
 /* Reads the SP ($29) register.  */
 #define MIPS16_INSN_READ_SP                0x00000800
-/* Reads the RA ($31) register.  */
-#define MIPS16_INSN_READ_31                0x00001000
-/* Reads the program counter.  */
-#define MIPS16_INSN_READ_PC                0x00002000
 /* Reads the general purpose register in MIPS16OP_*_REGR32.  */
 #define MIPS16_INSN_READ_GPR_X             0x00004000
-/* Is an unconditional branch insn. */
-#define MIPS16_INSN_UNCOND_BRANCH          0x00008000
-/* Is a conditional branch insn. */
-#define MIPS16_INSN_COND_BRANCH                    0x00010000
 
 /* The following flags have the same value for the mips16 opcode
    table:

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 5668f34f0b1b477d2cf8d4f6e4209846a888a7bf..32414a145ebea8f2c7d760c0b0c1a14408f6f0a8 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,11 @@
+2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
+       (WR_SP): Replace with...
+       (MOD_SP): ...this.
+       (mips16_opcodes): Update accordingly.
+       * mips-dis.c (print_insn_mips16): Likewise.
+
 2013-08-01  Richard Sandiford  <rdsandiford@googlemail.com>
 
        * mips16-opc.c (mips16_opcodes): Reformat.

diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index b7aa5513e64801b332d9eabf5cc17d6332a5f6c0..559359626d121159834781f1f99577d7c1e3a04d 100644 (file)
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -1749,15 +1749,15 @@ print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
          /* Figure out branch instruction type and delay slot information.  */
          if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
            info->branch_delay_insns = 1;
-         if ((op->pinfo & (INSN_UNCOND_BRANCH_DELAY
-                           | MIPS16_INSN_UNCOND_BRANCH)) != 0)
+         if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0
+             || (op->pinfo2 & INSN2_UNCOND_BRANCH) != 0)
            {
              if ((op->pinfo & INSN_WRITE_GPR_31) != 0)
                info->insn_type = dis_jsr;
              else
                info->insn_type = dis_branch;
            }
-         else if ((op->pinfo & MIPS16_INSN_COND_BRANCH) != 0)
+         else if ((op->pinfo2 & INSN2_COND_BRANCH) != 0)
            info->insn_type = dis_condbranch;
 
          return length;

diff --git a/opcodes/mips16-opc.c b/opcodes/mips16-opc.c
index 13de08d841bcf3e4c5f249607f62f69a3300eb41..b833e91f1e2aad1279a7a0ba243fe364329a1b80 100644 (file)
--- a/opcodes/mips16-opc.c
+++ b/opcodes/mips16-opc.c
@@ -143,14 +143,11 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
    the opcodes table.  */
 
 #define UBD     INSN_UNCOND_BRANCH_DELAY
-#define UBR    MIPS16_INSN_UNCOND_BRANCH
-#define CBR    MIPS16_INSN_COND_BRANCH
 
 #define WR_x   MIPS16_INSN_WRITE_X
 #define WR_y   MIPS16_INSN_WRITE_Y
 #define WR_z   MIPS16_INSN_WRITE_Z
 #define WR_T   MIPS16_INSN_WRITE_T
-#define WR_SP  MIPS16_INSN_WRITE_SP
 #define WR_31  MIPS16_INSN_WRITE_31
 #define WR_Y   MIPS16_INSN_WRITE_GPR_Y
 
@@ -159,8 +156,6 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
 #define RD_Z   MIPS16_INSN_READ_Z
 #define RD_T   MIPS16_INSN_READ_T
 #define RD_SP  MIPS16_INSN_READ_SP
-#define RD_31  MIPS16_INSN_READ_31
-#define RD_PC  MIPS16_INSN_READ_PC
 #define RD_X   MIPS16_INSN_READ_GPR_X
 
 #define WR_HI  INSN_WRITE_HI
@@ -171,6 +166,12 @@ decode_mips16_operand (char type, bfd_boolean extended_p)
 #define NODS   INSN_NO_DELAY_SLOT
 #define TRAP   INSN_NO_DELAY_SLOT
 
+#define MOD_SP INSN2_MOD_SP
+#define RD_31  INSN2_READ_GPR_31
+#define RD_PC  INSN2_READ_PC
+#define UBR    INSN2_UNCOND_BRANCH
+#define CBR    INSN2_COND_BRANCH
+
 #define I1     INSN_ISA1
 #define I3     INSN_ISA3
 #define I32    INSN_ISA32
@@ -181,26 +182,26 @@ const struct mips_opcode mips16_opcodes[] =
 {
 /* name,    args,      match,  mask,           pinfo,                  pinfo2, membership */
 {"nop",            "",         0x6500, 0xffff,         RD_Z,                   0,              I1,     0,      0 }, /* move $0,$Z */
-{"la",     "x,A",      0x0800, 0xf800,         WR_x|RD_PC,             0,              I1,     0,      0 },
+{"la",     "x,A",      0x0800, 0xf800,         WR_x,                   RD_PC,          I1,     0,      0 },
 {"abs",            "x,w",      0, (int) M_ABS,         INSN_MACRO,             0,              I1,     0,      0 },
 {"addiu",   "y,x,4",   0x4000, 0xf810,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"addiu",   "x,k",     0x4800, 0xf800,         WR_x|RD_x,              0,              I1,     0,      0 },
-{"addiu",   "S,K",     0x6300, 0xff00,         WR_SP|RD_SP,            0,              I1,     0,      0 },
-{"addiu",   "S,S,K",   0x6300, 0xff00,         WR_SP|RD_SP,            0,              I1,     0,      0 },
-{"addiu",   "x,P,V",   0x0800, 0xf800,         WR_x|RD_PC,             0,              I1,     0,      0 },
+{"addiu",   "S,K",     0x6300, 0xff00,         0,                      MOD_SP,         I1,     0,      0 },
+{"addiu",   "S,S,K",   0x6300, 0xff00,         0,                      MOD_SP,         I1,     0,      0 },
+{"addiu",   "x,P,V",   0x0800, 0xf800,         WR_x,                   RD_PC,          I1,     0,      0 },
 {"addiu",   "x,S,V",   0x0000, 0xf800,         WR_x|RD_SP,             0,              I1,     0,      0 },
 {"addu",    "z,v,y",   0xe001, 0xf803,         WR_z|RD_x|RD_y,         0,              I1,     0,      0 },
 {"addu",    "y,x,4",   0x4000, 0xf810,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"addu",    "x,k",     0x4800, 0xf800,         WR_x|RD_x,              0,              I1,     0,      0 },
-{"addu",    "S,K",     0x6300, 0xff00,         WR_SP|RD_SP,            0,              I1,     0,      0 },
-{"addu",    "S,S,K",   0x6300, 0xff00,         WR_SP|RD_SP,            0,              I1,     0,      0 },
-{"addu",    "x,P,V",   0x0800, 0xf800,         WR_x|RD_PC,             0,              I1,     0,      0 },
+{"addu",    "S,K",     0x6300, 0xff00,         0,                      MOD_SP,         I1,     0,      0 },
+{"addu",    "S,S,K",   0x6300, 0xff00,         0,                      MOD_SP,         I1,     0,      0 },
+{"addu",    "x,P,V",   0x0800, 0xf800,         WR_x,                   RD_PC,          I1,     0,      0 },
 {"addu",    "x,S,V",   0x0000, 0xf800,         WR_x|RD_SP,             0,              I1,     0,      0 },
 {"and",            "x,y",      0xe80c, 0xf81f,         WR_x|RD_x|RD_y,         0,              I1,     0,      0 },
-{"b",      "q",        0x1000, 0xf800,         UBR,                    0,              I1,     0,      0 },
+{"b",      "q",        0x1000, 0xf800,         0,                      UBR,            I1,     0,      0 },
 {"beq",            "x,y,p",    0, (int) M_BEQ,         INSN_MACRO,             0,              I1,     0,      0 },
 {"beq",     "x,I,p",   0, (int) M_BEQ_I,       INSN_MACRO,             0,              I1,     0,      0 },
-{"beqz",    "x,p",     0x2000, 0xf800,         CBR|RD_x,               0,              I1,     0,      0 },
+{"beqz",    "x,p",     0x2000, 0xf800,         RD_x,                   CBR,            I1,     0,      0 },
 {"bge",            "x,y,p",    0, (int) M_BGE,         INSN_MACRO,             0,              I1,     0,      0 },
 {"bge",     "x,I,p",   0, (int) M_BGE_I,       INSN_MACRO,             0,              I1,     0,      0 },
 {"bgeu",    "x,y,p",   0, (int) M_BGEU,        INSN_MACRO,             0,              I1,     0,      0 },
@@ -219,26 +220,26 @@ const struct mips_opcode mips16_opcodes[] =
 {"bltu",    "x,I,p",   0, (int) M_BLTU_I,      INSN_MACRO,             0,              I1,     0,      0 },
 {"bne",            "x,y,p",    0, (int) M_BNE,         INSN_MACRO,             0,              I1,     0,      0 },
 {"bne",     "x,I,p",   0, (int) M_BNE_I,       INSN_MACRO,             0,              I1,     0,      0 },
-{"bnez",    "x,p",     0x2800, 0xf800,         CBR|RD_x,               0,              I1,     0,      0 },
+{"bnez",    "x,p",     0x2800, 0xf800,         RD_x,                   CBR,            I1,     0,      0 },
 {"break",   "6",       0xe805, 0xf81f,         TRAP,                   0,              I1,     0,      0 },
-{"bteqz",   "p",       0x6000, 0xff00,         CBR|RD_T,               0,              I1,     0,      0 },
-{"btnez",   "p",       0x6100, 0xff00,         CBR|RD_T,               0,              I1,     0,      0 },
+{"bteqz",   "p",       0x6000, 0xff00,         RD_T,                   CBR,            I1,     0,      0 },
+{"btnez",   "p",       0x6100, 0xff00,         RD_T,                   CBR,            I1,     0,      0 },
 {"cmpi",    "x,U",     0x7000, 0xf800,         WR_T|RD_x,              0,              I1,     0,      0 },
 {"cmp",            "x,y",      0xe80a, 0xf81f,         WR_T|RD_x|RD_y,         0,              I1,     0,      0 },
 {"cmp",     "x,U",     0x7000, 0xf800,         WR_T|RD_x,              0,              I1,     0,      0 },
-{"dla",            "y,E",      0xfe00, 0xff00,         WR_y|RD_PC,             0,              I3,     0,      0 },
+{"dla",            "y,E",      0xfe00, 0xff00,         WR_y,                   RD_PC,          I3,     0,      0 },
 {"daddiu",  "y,x,4",   0x4010, 0xf810,         WR_y|RD_x,              0,              I3,     0,      0 },
 {"daddiu",  "y,j",     0xfd00, 0xff00,         WR_y|RD_y,              0,              I3,     0,      0 },
-{"daddiu",  "S,K",     0xfb00, 0xff00,         WR_SP|RD_SP,            0,              I3,     0,      0 },
-{"daddiu",  "S,S,K",   0xfb00, 0xff00,         WR_SP|RD_SP,            0,              I3,     0,      0 },
-{"daddiu",  "y,P,W",   0xfe00, 0xff00,         WR_y|RD_PC,             0,              I3,     0,      0 },
+{"daddiu",  "S,K",     0xfb00, 0xff00,         0,                      MOD_SP,         I3,     0,      0 },
+{"daddiu",  "S,S,K",   0xfb00, 0xff00,         0,                      MOD_SP,         I3,     0,      0 },
+{"daddiu",  "y,P,W",   0xfe00, 0xff00,         WR_y,                   RD_PC,          I3,     0,      0 },
 {"daddiu",  "y,S,W",   0xff00, 0xff00,         WR_y|RD_SP,             0,              I3,     0,      0 },
 {"daddu",   "z,v,y",   0xe000, 0xf803,         WR_z|RD_x|RD_y,         0,              I3,     0,      0 },
 {"daddu",   "y,x,4",   0x4010, 0xf810,         WR_y|RD_x,              0,              I3,     0,      0 },
 {"daddu",   "y,j",     0xfd00, 0xff00,         WR_y|RD_y,              0,              I3,     0,      0 },
-{"daddu",   "S,K",     0xfb00, 0xff00,         WR_SP|RD_SP,            0,              I3,     0,      0 },
-{"daddu",   "S,S,K",   0xfb00, 0xff00,         WR_SP|RD_SP,            0,              I3,     0,      0 },
-{"daddu",   "y,P,W",   0xfe00, 0xff00,         WR_y|RD_PC,             0,              I3,     0,      0 },
+{"daddu",   "S,K",     0xfb00, 0xff00,         0,                      MOD_SP,         I3,     0,      0 },
+{"daddu",   "S,S,K",   0xfb00, 0xff00,         0,                      MOD_SP,         I3,     0,      0 },
+{"daddu",   "y,P,W",   0xfe00, 0xff00,         WR_y,                   RD_PC,          I3,     0,      0 },
 {"daddu",   "y,S,W",   0xff00, 0xff00,         WR_y|RD_SP,             0,              I3,     0,      0 },
 {"ddiv",    "0,x,y",   0xe81e, 0xf81f,         RD_x|RD_y|WR_HI|WR_LO,  0,              I3,     0,      0 },
 {"ddiv",    "z,v,y",   0, (int) M_DDIV_3,      INSN_MACRO,             0,              I1,     0,      0 },
@@ -281,28 +282,28 @@ const struct mips_opcode mips16_opcodes[] =
 {"jal",            "a",        0x1800, 0xfc00,         UBD|WR_31,              0,              I1,     0,      0 },
 {"jalx",    "i",       0x1c00, 0xfc00,         UBD|WR_31,              0,              I1,     0,      0 },
 {"jr",     "x",        0xe800, 0xf8ff,         UBD|RD_x,               0,              I1,     0,      0 },
-{"jr",     "R",        0xe820, 0xffff,         UBD|RD_31,              0,              I1,     0,      0 },
+{"jr",     "R",        0xe820, 0xffff,         UBD,                    RD_31,          I1,     0,      0 },
 {"j",      "x",        0xe800, 0xf8ff,         UBD|RD_x,               0,              I1,     0,      0 },
-{"j",      "R",        0xe820, 0xffff,         UBD|RD_31,              0,              I1,     0,      0 },
+{"j",      "R",        0xe820, 0xffff,         UBD,                    RD_31,          I1,     0,      0 },
 /* MIPS16e compact branches.  We keep them near the ordinary branches
    so that we easily find them when converting a normal branch to a
    compact one.  */
-{"jalrc",   "x",       0xe8c0, 0xf8ff,         UBR|WR_31|RD_x|NODS,    0,              I32,    0,      0 },
-{"jalrc",   "R,x",     0xe8c0, 0xf8ff,         UBR|WR_31|RD_x|NODS,    0,              I32,    0,      0 },
-{"jrc",            "x",        0xe880, 0xf8ff,         UBR|RD_x|NODS,          0,              I32,    0,      0 },
-{"jrc",            "R",        0xe8a0, 0xffff,         UBR|RD_31|NODS,         0,              I32,    0,      0 },
+{"jalrc",   "x",       0xe8c0, 0xf8ff,         WR_31|RD_x|NODS,        UBR,            I32,    0,      0 },
+{"jalrc",   "R,x",     0xe8c0, 0xf8ff,         WR_31|RD_x|NODS,        UBR,            I32,    0,      0 },
+{"jrc",            "x",        0xe880, 0xf8ff,         RD_x|NODS,              UBR,            I32,    0,      0 },
+{"jrc",            "R",        0xe8a0, 0xffff,         NODS,                   UBR|RD_31,      I32,    0,      0 },
 {"lb",     "y,5(x)",   0x8000, 0xf800,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"lbu",            "y,5(x)",   0xa000, 0xf800,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"ld",     "y,D(x)",   0x3800, 0xf800,         WR_y|RD_x,              0,              I3,     0,      0 },
-{"ld",     "y,B",      0xfc00, 0xff00,         WR_y|RD_PC,             0,              I3,     0,      0 },
-{"ld",     "y,D(P)",   0xfc00, 0xff00,         WR_y|RD_PC,             0,              I3,     0,      0 },
+{"ld",     "y,B",      0xfc00, 0xff00,         WR_y,                   RD_PC,          I3,     0,      0 },
+{"ld",     "y,D(P)",   0xfc00, 0xff00,         WR_y,                   RD_PC,          I3,     0,      0 },
 {"ld",     "y,D(S)",   0xf800, 0xff00,         WR_y|RD_SP,             0,              I3,     0,      0 },
 {"lh",     "y,H(x)",   0x8800, 0xf800,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"lhu",            "y,H(x)",   0xa800, 0xf800,         WR_y|RD_x,              0,              I1,     0,      0 },
 {"li",     "x,U",      0x6800, 0xf800,         WR_x,                   0,              I1,     0,      0 },
 {"lw",     "y,W(x)",   0x9800, 0xf800,         WR_y|RD_x,              0,              I1,     0,      0 },
-{"lw",     "x,A",      0xb000, 0xf800,         WR_x|RD_PC,             0,              I1,     0,      0 },
-{"lw",     "x,V(P)",   0xb000, 0xf800,         WR_x|RD_PC,             0,              I1,     0,      0 },
+{"lw",     "x,A",      0xb000, 0xf800,         WR_x,                   RD_PC,          I1,     0,      0 },
+{"lw",     "x,V(P)",   0xb000, 0xf800,         WR_x,                   RD_PC,          I1,     0,      0 },
 {"lw",     "x,V(S)",   0x9000, 0xf800,         WR_x|RD_SP,             0,              I1,     0,      0 },
 {"lwu",     "y,W(x)",  0xb800, 0xf800,         WR_y|RD_x,              0,              I3,     0,      0 },
 {"mfhi",    "x",       0xe810, 0xf8ff,         WR_x|RD_HI,             0,              I1,     0,      0 },
@@ -321,8 +322,8 @@ const struct mips_opcode mips16_opcodes[] =
 {"remu",    "z,v,y",   0, (int) M_REMU_3,      INSN_MACRO,             0,              I1,     0,      0 },
 {"sb",     "y,5(x)",   0xc000, 0xf800,         RD_y|RD_x,              0,              I1,     0,      0 },
 {"sd",     "y,D(x)",   0x7800, 0xf800,         RD_y|RD_x,              0,              I3,     0,      0 },
-{"sd",     "y,D(S)",   0xf900, 0xff00,         RD_y|RD_PC,             0,              I3,     0,      0 },
-{"sd",     "R,C(S)",   0xfa00, 0xff00,         RD_31|RD_PC,            0,              I1,     0,      0 },
+{"sd",     "y,D(S)",   0xf900, 0xff00,         RD_y,                   RD_PC,          I3,     0,      0 },
+{"sd",     "R,C(S)",   0xfa00, 0xff00,         0,                      RD_PC|RD_31,    I1,     0,      0 },
 {"sh",     "y,H(x)",   0xc800, 0xf800,         RD_y|RD_x,              0,              I1,     0,      0 },
 {"sllv",    "y,x",     0xe804, 0xf81f,         WR_y|RD_y|RD_x,         0,              I1,     0,      0 },
 {"sll",            "x,w,<",    0x3000, 0xf803,         WR_x|RD_y,              0,              I1,     0,      0 },
@@ -344,11 +345,11 @@ const struct mips_opcode mips16_opcodes[] =
 {"subu",    "x,I",     0, (int) M_SUBU_I_2,    INSN_MACRO,             0,              I1,     0,      0 },
 {"sw",     "y,W(x)",   0xd800, 0xf800,         RD_y|RD_x,              0,              I1,     0,      0 },
 {"sw",     "x,V(S)",   0xd000, 0xf800,         RD_x|RD_SP,             0,              I1,     0,      0 },
-{"sw",     "R,V(S)",   0x6200, 0xff00,         RD_31|RD_SP,            0,              I1,     0,      0 },
+{"sw",     "R,V(S)",   0x6200, 0xff00,         RD_SP,                  RD_31,          I1,     0,      0 },
 {"xor",            "x,y",      0xe80e, 0xf81f,         WR_x|RD_x|RD_y,         0,              I1,     0,      0 },
   /* MIPS16e additions */
-{"restore", "M",       0x6400, 0xff80,         WR_31|RD_SP|WR_SP|NODS, 0,              I32,    0,      0 },
-{"save",    "m",       0x6480, 0xff80,         RD_31|RD_SP|WR_SP|NODS, 0,              I32,    0,      0 },
+{"restore", "M",       0x6400, 0xff80,         WR_31|NODS,             MOD_SP,         I32,    0,      0 },
+{"save",    "m",       0x6480, 0xff80,         NODS,                   MOD_SP|RD_31,   I32,    0,      0 },
 {"sdbbp",   "6",       0xe801, 0xf81f,         TRAP,                   0,              I32,    0,      0 },
 {"seb",            "x",        0xe891, 0xf8ff,         WR_x|RD_x,              0,              I32,    0,      0 },
 {"seh",            "x",        0xe8b1, 0xf8ff,         WR_x|RD_x,              0,              I32,    0,      0 },