[ARC][committed] Update int_vector_base aux register.

INT_VECTOR_BASE auxiliary register is available across all ARC
architectures.

xxxx-xx-xx  Claudiu Zissulescu <claziss@gmail.com>

	* arc-regs.h (int_vector_base): Make it available for all ARC
	CPUs.

Signed-off-by: Claudiu Zissulescu <claziss@gmail.com>

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 73091b9e61d16bef786188b8c2238cbc5bfaa591..5d8357864185ceae4a8ab50d8380f1d2ef7464d5 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2020-02-25  Claudiu Zissulescu <claziss@gmail.com>
+
+       * arc-regs.h (int_vector_base): Make it available for all ARC
+       CPUs.
+
 2020-02-20  Nelson Chu  <nelson.chu@sifive.com>
 
        * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is

diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h
index a1d98bf17942792e1f7a7cd133c95912f81753e0..4494a0630a1c7f9d561aed538771daf54ee622b3 100644 (file)
--- a/opcodes/arc-regs.h
+++ b/opcodes/arc-regs.h
@@ -71,8 +71,7 @@ DEF (0x21,  ARC_OPCODE_ARCALL,  NONE, count0)
 DEF (0x22,  ARC_OPCODE_ARCALL,  NONE, control0)
 DEF (0x23,  ARC_OPCODE_ARCALL,  NONE, limit0)
 DEF (0x24,  ARC_OPCODE_ARCV1,   NONE, pcport)
-DEF (0x25,  ARC_OPCODE_ARC700,  NONE, int_vector_base)
-DEF (0x25,  ARC_OPCODE_ARCV2,   NONE, int_vector_base)
+DEF (0x25,  ARC_OPCODE_ARCALL,  NONE, int_vector_base)
 DEF (0x26,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_mode)
 DEF (0x27,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm0)
 DEF (0x28,  ARC_OPCODE_ARC600,  NONE, aux_vbfdw_bm1)