Update doc with max cascade chain of 20

diff --git a/passes/pmgen/xilinx_dsp.cc b/passes/pmgen/xilinx_dsp.cc
index 6ce5f2e166ba1824849245860d2203bc11b0dea0..11c7e5ea804f4f6cee84f6367ba7f42036a6b2af 100644 (file)
--- a/passes/pmgen/xilinx_dsp.cc
+++ b/passes/pmgen/xilinx_dsp.cc
@@ -576,8 +576,10 @@ struct XilinxDspPass : public Pass {
                log("Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'\n");
                log("connections (optionally, where 'P' is right-shifted by 17-bits and used as an\n");
                log("input to the post-adder -- a pattern common for summing partial products to\n");
-               log("implement wide multipliers). Initial support also exists for similar cascading\n");
-               log("for AREG and BREG using '[AB]OUT' -> '[AB]IN'.\n");
+               log("implement wide multipliers). Limited support also exists for similar cascading\n");
+               log("for A and B using '[AB]COUT' -> '[AB]CIN'. Currently, cascade chains are limited\n");
+               log("to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series\n");
+               log("device.\n");
                log("\n");
                log("\n");
                log("Experimental feature: addition/subtractions less than 12 or 24 bits with the\n");