soc/interconnect/stream: expose depth on SyncFIFO

diff --git a/litex/soc/interconnect/stream.py b/litex/soc/interconnect/stream.py
index 4c56b06ef94cedea0a6dc43f8dc7c2a488ffb87d..bc6793cacca2e41a807595911355f1d900518182 100644 (file)
--- a/litex/soc/interconnect/stream.py
+++ b/litex/soc/interconnect/stream.py
@@ -99,6 +99,7 @@ class SyncFIFO(_FIFOWrapper):
             self,
             fifo.SyncFIFOBuffered if buffered else fifo.SyncFIFO,
             layout, depth)
+        self.depth = self.fifo.depth
         self.level = self.fifo.level