i965: Stop doing our optimization on a copy of the GLSL IR.

The original intent was that we'd keep a driver-private copy, and there
would be the normal copy for swrast to make use of without the tuning (or
anything more invasive we might do) specific to i965.  Only, we don't
generate swrast code any more, because swrast can't render current shaders
anyway.  Thus, our private copy is rather a waste, and we can just do our
backend-specific operations on the linked shader.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h
index e19ffc07152423a5f5c8c048b2b746731757afb2..9c516469cf6301beaa4fae9246a759438731815e 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -320,9 +320,6 @@ struct brw_shader {
    struct gl_shader base;
 
    bool compiled_once;
-
-   /** Shader IR transformed for native compile, at link time. */
-   struct exec_list *ir;
 };
 
 /* Note: If adding fields that need anything besides a normal memcmp() for

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp
index baf9220125cebab17083dc9c97f079ff6df7b1b3..3536cbeecc5207bad06efc0a359dd8301f1adb45 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3156,7 +3156,7 @@ fs_visitor::run()
        * functions called "main").
        */
       if (shader) {
-         foreach_list(node, &*shader->ir) {
+         foreach_list(node, &*shader->base.ir) {
             ir_instruction *ir = (ir_instruction *)node;
             base_ir = ir;
             this->result = reg_undef;
@@ -3305,7 +3305,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct brw_wm_compile *c,
    if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
       if (prog) {
          printf("GLSL IR for native fragment shader %d:\n", prog->Name);
-         _mesa_print_ir(shader->ir, NULL);
+         _mesa_print_ir(shader->base.ir, NULL);
          printf("\n\n");
       } else {
          printf("ARB_fragment_program %d ir for native fragment shader\n",

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index cf9ca4bbf91cd142f3e17bf897704b7215381b1e..5752348be65f36e59080303fb84be4058c542fa6 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -135,24 +135,18 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
 
       _mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
 
-      void *mem_ctx = ralloc_context(NULL);
       bool progress;
 
-      if (shader->ir)
-        ralloc_free(shader->ir);
-      shader->ir = new(shader) exec_list;
-      clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
-
       /* lower_packing_builtins() inserts arithmetic instructions, so it
        * must precede lower_instructions().
        */
-      brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->ir);
-      do_mat_op_to_vec(shader->ir);
+      brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader->base.ir);
+      do_mat_op_to_vec(shader->base.ir);
       const int bitfield_insert = brw->gen >= 7
                                   ? BITFIELD_INSERT_TO_BFM_BFI
                                   : 0;
       const int lrp_to_arith = brw->gen < 6 ? LRP_TO_ARITH : 0;
-      lower_instructions(shader->ir,
+      lower_instructions(shader->base.ir,
                         MOD_TO_FRACT |
                         DIV_TO_MUL_RCP |
                         SUB_TO_ADD_NEG |
@@ -166,17 +160,17 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
        * if-statements need to be flattened.
        */
       if (brw->gen < 6)
-        lower_if_to_cond_assign(shader->ir, 16);
-
-      do_lower_texture_projection(shader->ir);
-      brw_lower_texture_gradients(brw, shader->ir);
-      do_vec_index_to_cond_assign(shader->ir);
-      lower_vector_insert(shader->ir, true);
-      brw_do_cubemap_normalize(shader->ir);
-      brw_do_lower_offset_arrays(shader->ir);
-      brw_do_lower_unnormalized_offset(shader->ir);
-      lower_noise(shader->ir);
-      lower_quadop_vector(shader->ir, false);
+        lower_if_to_cond_assign(shader->base.ir, 16);
+
+      do_lower_texture_projection(shader->base.ir);
+      brw_lower_texture_gradients(brw, shader->base.ir);
+      do_vec_index_to_cond_assign(shader->base.ir);
+      lower_vector_insert(shader->base.ir, true);
+      brw_do_cubemap_normalize(shader->base.ir);
+      brw_do_lower_offset_arrays(shader->base.ir);
+      brw_do_lower_unnormalized_offset(shader->base.ir);
+      lower_noise(shader->base.ir);
+      lower_quadop_vector(shader->base.ir, false);
 
       bool input = true;
       bool output = stage == MESA_SHADER_FRAGMENT;
@@ -184,7 +178,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
       bool uniform = false;
 
       bool lowered_variable_indexing =
-         lower_variable_index_to_cond_assign(shader->ir,
+         lower_variable_index_to_cond_assign(shader->base.ir,
                                              input, output, temp, uniform);
 
       if (unlikely(brw->perf_debug && lowered_variable_indexing)) {
@@ -193,23 +187,23 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
       }
 
       /* FINISHME: Do this before the variable index lowering. */
-      lower_ubo_reference(&shader->base, shader->ir);
+      lower_ubo_reference(&shader->base, shader->base.ir);
 
       do {
         progress = false;
 
         if (stage == MESA_SHADER_FRAGMENT) {
-           brw_do_channel_expressions(shader->ir);
-           brw_do_vector_splitting(shader->ir);
+           brw_do_channel_expressions(shader->base.ir);
+           brw_do_vector_splitting(shader->base.ir);
         }
 
-        progress = do_lower_jumps(shader->ir, true, true,
+        progress = do_lower_jumps(shader->base.ir, true, true,
                                   true, /* main return */
                                   false, /* continue */
                                   false /* loops */
                                   ) || progress;
 
-        progress = do_common_optimization(shader->ir, true, true, 32,
+        progress = do_common_optimization(shader->base.ir, true, true, 32,
                                            &ctx->ShaderCompilerOptions[stage])
           || progress;
       } while (progress);
@@ -221,7 +215,7 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
        * too late.  At that point, the values for the built-in uniforms won't
        * get sent to the shader.
        */
-      foreach_list(node, shader->ir) {
+      foreach_list(node, shader->base.ir) {
         ir_variable *var = ((ir_instruction *) node)->as_variable();
 
         if ((var == NULL) || (var->data.mode != ir_var_uniform)
@@ -237,12 +231,9 @@ brw_link_shader(struct gl_context *ctx, struct gl_shader_program *shProg)
         }
       }
 
-      validate_ir_tree(shader->ir);
-
-      reparent_ir(shader->ir, shader->ir);
-      ralloc_free(mem_ctx);
+      validate_ir_tree(shader->base.ir);
 
-      do_set_program_inouts(shader->ir, prog, shader->base.Stage);
+      do_set_program_inouts(shader->base.ir, prog, shader->base.Stage);
 
       prog->SamplersUsed = shader->base.active_samplers;
       _mesa_update_shader_textures_used(shProg, prog);

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index fb57707513b62ed565fdb31933ffc765c34867f2..9d3735a1504ed37a05aaa10d9b1ae287497574ab 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1540,7 +1540,7 @@ vec4_visitor::run()
     * functions called "main").
     */
    if (shader) {
-      visit_instructions(shader->ir);
+      visit_instructions(shader->base.ir);
    } else {
       emit_program_code();
    }
@@ -1654,7 +1654,7 @@ brw_vs_emit(struct brw_context *brw,
    if (unlikely(INTEL_DEBUG & DEBUG_VS)) {
       if (prog) {
          printf("GLSL IR for native vertex shader %d:\n", prog->Name);
-         _mesa_print_ir(shader->ir, NULL);
+         _mesa_print_ir(shader->base.ir, NULL);
          printf("\n\n");
       } else {
          printf("ARB_vertex_program %d for native vertex shader\n",

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
index c93459d28a73d04ae8dd9f834795a7db964e6749..5d5b16904776f44b1d60e7d3cc8a6154da9662de 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp
@@ -546,7 +546,7 @@ brw_gs_emit(struct brw_context *brw,
 
    if (unlikely(INTEL_DEBUG & DEBUG_GS)) {
       printf("GLSL IR for native geometry shader %d:\n", prog->Name);
-      _mesa_print_ir(shader->ir, NULL);
+      _mesa_print_ir(shader->base.ir, NULL);
       printf("\n\n");
    }