(no commit message)

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index f1ba46b602d8f5654944310db4b4223431ed9dcf..091abd02a28f233c3b9915bd282d97669f89b923 100644 (file)
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -612,6 +612,7 @@ if VLSET and cond_ok = VSb then
 # Example Shader code
 
 ```
+// assume f() g() or h() modify a and/or b
 while(a > 2) {
     if(b < 5)
         f();
@@ -627,13 +628,18 @@ which compiles to something like:
 vec<i32> a, b;
 // ...
 pred loop_pred = a > 2;
+// loop continues while any of a elements greater than 2
 while(loop_pred.any()) {
+    // vector of predicate bits
     pred if_pred = loop_pred & (b < 5);
+    // only call f() if at least 1 bit set
     if(if_pred.any()) {
         f(if_pred);
     }
 label1:
+    // loop mask ANDs with inverted if-test
     pred else_pred = loop_pred & ~if_pred;
+    // only call g() if at least 1 bit set
     if(else_pred.any()) {
         g(else_pred);
     }
@@ -644,8 +650,8 @@ label1:
 which will end up as:
 
 ```
-   sv.cmpi CR60.v a.v, 2      # vector compare a into CR60 vector
-   sv.crweird r30, CR60.GT # transfer GT vector to r30
+   # start from while loop test point
+   b looptest
 while_loop:
    sv.cmpi CR80.v, b.v, 5     # vector compare b into CR64 Vector
    sv.bc/m=r30/~ALL/sz CR80.v.LT skip_f # skip when none
@@ -663,5 +669,9 @@ skip_f:
 skip_g:
    # conditionally call h(r30) if any loop pred set
    sv.bclr/m=r30/~ALL/sz BO[1]=1 h()
+looptest:
+   sv.cmpi CR60.v a.v, 2      # vector compare a into CR60 vector
+   sv.crweird r30, CR60.GT # transfer GT vector to r30
    sv.bc/m=r30/~ALL/sz BO[1]=1 while_loop
+end:
 ```