(no commit message)

diff --git a/openpower/sv/svp_rewrite/svp64.mdwn b/openpower/sv/svp_rewrite/svp64.mdwn
index dda30fd4f5ed2ab50ebc5cc9fd4b7984b3eada77..dd44f4c9cee8b0ebe48ef0e2751506ec64832f07 100644 (file)
--- a/openpower/sv/svp_rewrite/svp64.mdwn
+++ b/openpower/sv/svp_rewrite/svp64.mdwn
@@ -46,7 +46,7 @@ Twin Predication (1 src, 1 dest):
 
 ## Predicate MASK Encoding
 
-One bit indicates the mode: CR or Int predication.   The two types may not be mixed.
+One bit (`MASKMODE`) indicates the mode: CR or Int predication.   The two types may not be mixed.
 
 Integer Twin predication has a second set if 3 bits that uses the same encoding thus allowing either the same register (r3 or r10) to be used for both src and dest, or different regs (one for src, one for dest).