arch-arm: Add AArch32 SVC Semihosting interface

AArch32 Svc instruction is now able to issue Arm Semihosting commands as
the AArch64 counterpart in either Arm and Thumb mode.

Change-Id: Ibe47ac23d0c26f3f819cc0e2b3ee874b5cdbb3d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8371
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index cf3d0e00fe46d5bc71fc4255a0ff9690124b3429..566ea4b9d1bf3d1f7289b25965feb8d574f5ea0f 100644 (file)
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -40,15 +40,26 @@
 let {{
 
     svcCode = '''
-    fault = std::make_shared<SupervisorCall>(machInst, imm);
+    ThreadContext *tc = xc->tcBase();
+
+    const auto semihost_imm = Thumb? 0xAB : 0x123456;
+
+    if (ArmSystem::haveSemihosting(tc) && imm == semihost_imm) {
+        R0 = ArmSystem::callSemihosting32(tc, R0, R1);
+    } else {
+        fault = std::make_shared<SupervisorCall>(machInst, imm);
+    }
     '''
 
     svcIop = InstObjParams("svc", "Svc", "ImmOp",
                            { "code": svcCode,
-                             "predicate_test": predicateTest },
-                           ["IsSyscall", "IsNonSpeculative", "IsSerializeAfter"])
+                             "predicate_test": predicateTest,
+                             "thumb_semihost": '0xAB',
+                             "arm_semihost": '0x123456' },
+                           ["IsSyscall", "IsNonSpeculative",
+                            "IsSerializeAfter"])
     header_output = ImmOpDeclare.subst(svcIop)
-    decoder_output = ImmOpConstructor.subst(svcIop)
+    decoder_output = SemihostConstructor.subst(svcIop)
     exec_output = PredOpExecute.subst(svcIop)
 
     smcCode = '''