aarch64: Fix mismatched SVE predicate modes [PR94606]

For this testcase we ended up generating the invalid rtl:

(insn 10 9 11 2 (set (reg:VNx16BI 105)
        (and:VNx16BI (xor:VNx16BI (reg:VNx8BI 103)
                (reg:VNx16BI 104))
            (reg:VNx16BI 104))) "/tmp/bar.c":9:12 -1
     (nil))

Fixed by taking the VNx16BI lowpart.  It's safe to do that here because
the gp (r104) masks out the extra odd-indexed bits.

2020-04-16  Richard Sandiford  <richard.sandiford@arm.com>

gcc/
	PR target/94606
	* config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
	the VNx16BI lowpart of the recursively-generated constant.

gcc/testsuite/
	PR target/94606
	* gcc.dg/vect/pr94606.c: New test.

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 9e499ec9c86c800f506b0327ce4e6cb3e4bfc357..0c7dad08637516890f3338b7496334da39d46aea 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,9 @@
+2020-04-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/94606
+       * config/aarch64/aarch64.c (aarch64_expand_sve_const_pred_eor): Take
+       the VNx16BI lowpart of the recursively-generated constant.
+
 2020-04-16  Martin Liska  <mliska@suse.cz>
            Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4af562a81ea760891fac3cf7101b8bf887fe7a0d..d0a41c286cdfde9759fcbad1b2e2367037f0a832 100644 (file)
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -4742,6 +4742,7 @@ aarch64_expand_sve_const_pred_eor (rtx target, rtx_vector_builder &builder,
   /* EOR the result with an ELT_SIZE PTRUE.  */
   rtx mask = aarch64_ptrue_all (elt_size);
   mask = force_reg (VNx16BImode, mask);
+  inv = gen_lowpart (VNx16BImode, inv);
   target = aarch64_target_reg (target, VNx16BImode);
   emit_insn (gen_aarch64_pred_z (XOR, VNx16BImode, target, mask, inv, mask));
   return target;

diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 94d2312022de30db844246c5e3b28d6727a46f93..72bed4064e561ef8e96c70c7e49dff955364c245 100644 (file)
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,8 @@
+2020-04-16  Richard Sandiford  <richard.sandiford@arm.com>
+
+       PR target/94606
+       * gcc.dg/vect/pr94606.c: New test.
+
 2020-04-16  Martin Liska  <mliska@suse.cz>
            Jakub Jelinek  <jakub@redhat.com>
 

diff --git a/gcc/testsuite/gcc.dg/vect/pr94606.c b/gcc/testsuite/gcc.dg/vect/pr94606.c
new file mode 100644 (file)
index 0000000..f0e7c4c
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr94606.c
@@ -0,0 +1,13 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-march=armv8.2-a+sve -msve-vector-bits=256" { target aarch64*-*-* } } */
+
+const short mask[] = { 0, 0, 0, 0, 0, 0, 0, 0,
+                      0, 0, 0, 1, 1, 1, 1, 1 };
+
+int
+foo (short *restrict x, short *restrict y)
+{
+  for (int i = 0; i < 16; ++i)
+    if (mask[i])
+      x[i] += y[i];
+}