+2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
+
+ * config/tc-arm.c (M_MNEM_vaddlv, M_MNEM_vaddlva, M_MNEM_vaddv,
+ M_MNEM_vaddva): New instruction encodings.
+ (mve_encode_rq): New encoding helper function.
+ (do_mve_vaddlv): New encoding function.
+ (do_mve_vaddv): New encoding function.
+ * testsuite/gas/arm/mve-vaddlv-bad.d: New test.
+ * testsuite/gas/arm/mve-vaddlv-bad.l: New test.
+ * testsuite/gas/arm/mve-vaddlv-bad.s: New test.
+ * testsuite/gas/arm/mve-vaddv-bad.d: New test.
+ * testsuite/gas/arm/mve-vaddv-bad.l: New test.
+ * testsuite/gas/arm/mve-vaddv-bad.s: New test.
+
2019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
* config/tc-arm.c (M_MNEM_vadc, M_MNEM_vadci, M_MNEM_vbrsr):
#define M_MNEM_vadc 0xee300f00
#define M_MNEM_vadci 0xee301f00
#define M_MNEM_vbrsr 0xfe011e60
+#define M_MNEM_vaddlv 0xee890f00
+#define M_MNEM_vaddlva 0xee890f20
+#define M_MNEM_vaddv 0xeef10f00
+#define M_MNEM_vaddva 0xeef10f20
/* Neon instruction encoder helpers. */
X(3, (D, D, S), DOUBLE), \
X(3, (Q, Q, S), QUAD), \
X(3, (Q, Q, R), QUAD), \
+ X(3, (R, R, Q), QUAD), \
+ X(2, (R, Q), QUAD), \
X(2, (D, D), DOUBLE), \
X(2, (Q, Q), QUAD), \
X(2, (D, S), DOUBLE), \
inst.is_neon = 1;
}
+static void
+mve_encode_rq (unsigned bit28, unsigned size)
+{
+ inst.instruction |= bit28 << 28;
+ inst.instruction |= neon_logbits (size) << 18;
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= LOW4 (inst.operands[1].reg);
+ inst.is_neon = 1;
+}
/* Encode insns with bit pattern:
inst.is_neon = 1;
}
+static void
+do_mve_vaddlv (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_RRQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (3, rs, N_EQK, N_EQK, N_S32 | N_U32 | N_KEY);
+
+ if (et.type == NT_invtype)
+ first_error (BAD_EL_TYPE);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
+
+ inst.instruction |= (et.type == NT_unsigned) << 28;
+ inst.instruction |= inst.operands[1].reg << 19;
+ inst.instruction |= inst.operands[0].reg << 12;
+ inst.instruction |= inst.operands[2].reg;
+ inst.is_neon = 1;
+}
+
static void
do_neon_dyadic_if_su (void)
{
}
}
+static void
+do_mve_vaddv (void)
+{
+ enum neon_shape rs = neon_select_shape (NS_RQ, NS_NULL);
+ struct neon_type_el et
+ = neon_check_type (2, rs, N_EQK, N_SU_32 | N_KEY);
+
+ if (et.type == NT_invtype)
+ first_error (BAD_EL_TYPE);
+
+ if (inst.cond > COND_ALWAYS)
+ inst.pred_insn_type = INSIDE_VPT_INSN;
+ else
+ inst.pred_insn_type = MVE_OUTSIDE_PRED_INSN;
+
+ constraint (inst.operands[1].reg > 14, MVE_BAD_QREG);
+
+ mve_encode_rq (et.type == NT_unsigned, et.size);
+}
+
static void
do_mve_vadc (void)
{
mCEF(vmovnt, _vmovnt, 2, (RMQ, RMQ), mve_movn),
mCEF(vmovnb, _vmovnb, 2, (RMQ, RMQ), mve_movn),
mCEF(vbrsr, _vbrsr, 3, (RMQ, RMQ, RR), mve_vbrsr),
+ mCEF(vaddlv, _vaddlv, 3, (RRe, RRo, RMQ), mve_vaddlv),
+ mCEF(vaddlva, _vaddlva, 3, (RRe, RRo, RMQ), mve_vaddlv),
+ mCEF(vaddv, _vaddv, 2, (RRe, RMQ), mve_vaddv),
+ mCEF(vaddva, _vaddva, 2, (RRe, RMQ), mve_vaddv),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_vfp_ext_v1
--- /dev/null
+#name: Bad MVE VADDLV instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vaddlv-bad.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Error: bad type in SIMD instruction -- `vaddlv.i32 r0,r1,q0'
+[^:]*:14: Error: bad type in SIMD instruction -- `vaddlv.f32 r0,r1,q0'
+[^:]*:15: Error: bad type in SIMD instruction -- `vaddlv.s8 r0,r1,q0'
+[^:]*:16: Error: bad type in SIMD instruction -- `vaddlv.s16 r0,r1,q0'
+[^:]*:17: Error: bad type in SIMD instruction -- `vaddlv.s64 r0,r1,q0'
+[^:]*:18: Error: bad type in SIMD instruction -- `vaddlv.u8 r0,r1,q0'
+[^:]*:19: Error: bad type in SIMD instruction -- `vaddlv.u16 r0,r1,q0'
+[^:]*:20: Error: bad type in SIMD instruction -- `vaddlv.u64 r0,r1,q0'
+[^:]*:21: Error: bad type in SIMD instruction -- `vaddlva.i32 r0,r1,q0'
+[^:]*:22: Error: bad type in SIMD instruction -- `vaddlva.f32 r0,r1,q0'
+[^:]*:23: Error: bad type in SIMD instruction -- `vaddlva.s8 r0,r1,q0'
+[^:]*:24: Error: bad type in SIMD instruction -- `vaddlva.s16 r0,r1,q0'
+[^:]*:25: Error: bad type in SIMD instruction -- `vaddlva.s64 r0,r1,q0'
+[^:]*:26: Error: bad type in SIMD instruction -- `vaddlva.u8 r0,r1,q0'
+[^:]*:27: Error: bad type in SIMD instruction -- `vaddlva.u16 r0,r1,q0'
+[^:]*:28: Error: bad type in SIMD instruction -- `vaddlva.u64 r0,r1,q0'
+[^:]*:29: Error: Odd register not allowed here -- `vaddlv.s32 r1,r3,q0'
+[^:]*:30: Error: Even register not allowed here -- `vaddlva.s32 r0,r2,q0'
+[^:]*:31: Warning: instruction is UNPREDICTABLE with SP operand
+[^:]*:33: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
+[^:]*:34: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
+[^:]*:36: Error: syntax error -- `vaddlveq.s32 r0,r1,q0'
+[^:]*:37: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvt.s32 r0,r1,q0'
+[^:]*:39: Error: instruction missing MVE vector predication code -- `vaddlv.s32 r0,r1,q0'
+[^:]*:41: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
+[^:]*:42: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
+[^:]*:44: Error: syntax error -- `vaddlvaeq.s32 r0,r1,q0'
+[^:]*:45: Error: vector predicated instruction should be in VPT/VPST block -- `vaddlvat.s32 r0,r1,q0'
+[^:]*:47: Error: instruction missing MVE vector predication code -- `vaddlva.s32 r0,r1,q0'
--- /dev/null
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp mnem, vaddlv.s32, vaddlva.u32
+it \cond
+\mnem r0, r1, q0
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vaddlv.i32 r0, r1, q0
+vaddlv.f32 r0, r1, q0
+vaddlv.s8 r0, r1, q0
+vaddlv.s16 r0, r1, q0
+vaddlv.s64 r0, r1, q0
+vaddlv.u8 r0, r1, q0
+vaddlv.u16 r0, r1, q0
+vaddlv.u64 r0, r1, q0
+vaddlva.i32 r0, r1, q0
+vaddlva.f32 r0, r1, q0
+vaddlva.s8 r0, r1, q0
+vaddlva.s16 r0, r1, q0
+vaddlva.s64 r0, r1, q0
+vaddlva.u8 r0, r1, q0
+vaddlva.u16 r0, r1, q0
+vaddlva.u64 r0, r1, q0
+vaddlv.s32 r1, r3, q0
+vaddlva.s32 r0, r2, q0
+vaddlv.s32 r0, sp, q0
+it eq
+vaddlveq.s32 r0, r1, q0
+vaddlveq.s32 r0, r1, q0
+vpst
+vaddlveq.s32 r0, r1, q0
+vaddlvt.s32 r0, r1, q0
+vpst
+vaddlv.s32 r0, r1, q0
+it eq
+vaddlvaeq.s32 r0, r1, q0
+vaddlvaeq.s32 r0, r1, q0
+vpst
+vaddlvaeq.s32 r0, r1, q0
+vaddlvat.s32 r0, r1, q0
+vpst
+vaddlva.s32 r0, r1, q0
--- /dev/null
+#name: bad MVE VADDV instructions
+#as: -march=armv8.1-m.main+mve.fp
+#error_output: mve-vaddv-bad.l
+
+.*: +file format .*arm.*
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:12: Warning: instruction is UNPREDICTABLE in an IT block
+[^:]*:13: Error: bad type in SIMD instruction -- `vaddv.i32 r0,q0'
+[^:]*:14: Error: bad type in SIMD instruction -- `vaddv.f32 r0,q0'
+[^:]*:15: Error: bad type in SIMD instruction -- `vaddv.s64 r0,q0'
+[^:]*:16: Error: bad type in SIMD instruction -- `vaddv.u64 r0,q0'
+[^:]*:17: Error: bad type in SIMD instruction -- `vaddva.i32 r0,q0'
+[^:]*:18: Error: bad type in SIMD instruction -- `vaddva.f32 r0,q0'
+[^:]*:19: Error: bad type in SIMD instruction -- `vaddva.s64 r0,q0'
+[^:]*:20: Error: bad type in SIMD instruction -- `vaddva.u64 r0,q0'
+[^:]*:21: Error: Odd register not allowed here -- `vaddv.s32 r1,q0'
+[^:]*:23: Error: syntax error -- `vaddveq.s32 r0,q0'
+[^:]*:24: Error: syntax error -- `vaddveq.s32 r0,q0'
+[^:]*:26: Error: syntax error -- `vaddveq.s32 r0,q0'
+[^:]*:27: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvt.s32 r0,q0'
+[^:]*:29: Error: instruction missing MVE vector predication code -- `vaddv.s32 r0,q0'
+[^:]*:31: Error: syntax error -- `vaddvaeq.s32 r0,q0'
+[^:]*:32: Error: syntax error -- `vaddvaeq.s32 r0,q0'
+[^:]*:34: Error: syntax error -- `vaddvaeq.s32 r0,q0'
+[^:]*:35: Error: vector predicated instruction should be in VPT/VPST block -- `vaddvat.s32 r0,q0'
+[^:]*:37: Error: instruction missing MVE vector predication code -- `vaddva.s32 r0,q0'
--- /dev/null
+.macro cond
+.irp cond, eq, ne, gt, ge, lt, le
+.irp mnem, vaddv.s32, vaddva.u32
+it \cond
+\mnem r0, q0
+.endr
+.endr
+.endm
+
+.syntax unified
+.thumb
+cond
+vaddv.i32 r0, q0
+vaddv.f32 r0, q0
+vaddv.s64 r0, q0
+vaddv.u64 r0, q0
+vaddva.i32 r0, q0
+vaddva.f32 r0, q0
+vaddva.s64 r0, q0
+vaddva.u64 r0, q0
+vaddv.s32 r1, q0
+it eq
+vaddveq.s32 r0, q0
+vaddveq.s32 r0, q0
+vpst
+vaddveq.s32 r0, q0
+vaddvt.s32 r0, q0
+vpst
+vaddv.s32 r0, q0
+it eq
+vaddvaeq.s32 r0, q0
+vaddvaeq.s32 r0, q0
+vpst
+vaddvaeq.s32 r0, q0
+vaddvat.s32 r0, q0
+vpst
+vaddva.s32 r0, q0
projects / binutils-gdb.git / commitdiff