Revise spelling: RISK5 -> RISC-V

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index b6c10412bf1d87a7fbafa098b7fb296ad87e5707..89fbcfe1acdfe7ca66a49ae67c24449846866016 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -137,7 +137,7 @@ Actual Vector Processor Architectures and ISAs:
 * Cray ISA
   <http://www.bitsavers.org/pdf/cray/CRAY_Y-MP/HR-04001-0C_Cray_Y-MP_Computer_Systems_Functional_Description_Jun90.pdf>
 
-* RISK5 RVV
+* RISC-V RVV
   <https://github.com/riscv/riscv-v-spec>
 
 * MRISC32 ISA Manual (under active development)