gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 14:38:52
-gem5 started Mar 26 2013 23:18:50
+gem5 compiled Mar 28 2013 09:43:29
+gem5 started Mar 28 2013 09:43:43
gem5 executing on ribera.cs.wisc.edu
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual -re tests/run.py build/ALPHA/tests/opt/long/fs/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
0: system.tsunami.io.rtc: Real-time clock set to Thu Jan 1 00:00:00 2009
info: Entering event queue @ 0. Starting simulation...
info: Launching CPU 1 @ 110215000
-Exiting @ tick 1900727015500 because m5_exit instruction encountered
+Exiting @ tick 1900727697500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 1.900727 # Number of seconds simulated
-sim_ticks 1900727015500 # Number of ticks simulated
-final_tick 1900727015500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 1.900728 # Number of seconds simulated
+sim_ticks 1900727697500 # Number of ticks simulated
+final_tick 1900727697500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 47037 # Simulator instruction rate (inst/s)
-host_op_rate 47037 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1570523818 # Simulator tick rate (ticks/s)
-host_mem_usage 354648 # Number of bytes of host memory used
-host_seconds 1210.25 # Real time elapsed on the host
-sim_insts 56926994 # Number of instructions simulated
-sim_ops 56926994 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::cpu0.inst 854592 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 24596416 # Number of bytes read from this memory
+host_inst_rate 95395 # Simulator instruction rate (inst/s)
+host_op_rate 95395 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 3185234659 # Simulator tick rate (ticks/s)
+host_mem_usage 355712 # Number of bytes of host memory used
+host_seconds 596.73 # Real time elapsed on the host
+sim_insts 56925219 # Number of instructions simulated
+sim_ops 56925219 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::cpu0.inst 854208 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 24595840 # Number of bytes read from this memory
system.physmem.bytes_read::tsunami.ide 2651904 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 123456 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 541184 # Number of bytes read from this memory
-system.physmem.bytes_read::total 28767552 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 854592 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 123456 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 978048 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 7730624 # Number of bytes written to this memory
-system.physmem.bytes_written::total 7730624 # Number of bytes written to this memory
-system.physmem.num_reads::cpu0.inst 13353 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 384319 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu1.inst 123328 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 541952 # Number of bytes read from this memory
+system.physmem.bytes_read::total 28767232 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 854208 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 123328 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 977536 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 7730048 # Number of bytes written to this memory
+system.physmem.bytes_written::total 7730048 # Number of bytes written to this memory
+system.physmem.num_reads::cpu0.inst 13347 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 384310 # Number of read requests responded to by this memory
system.physmem.num_reads::tsunami.ide 41436 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 1929 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 8456 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 449493 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 120791 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 120791 # Number of write requests responded to by this memory
-system.physmem.bw_read::cpu0.inst 449613 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 12940531 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu1.inst 1927 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 8468 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 449488 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 120782 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 120782 # Number of write requests responded to by this memory
+system.physmem.bw_read::cpu0.inst 449411 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 12940223 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::tsunami.ide 1395205 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 64952 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 284725 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 15135026 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 449613 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 64952 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 514565 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 4067193 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 4067193 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 4067193 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 449613 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 12940531 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 64885 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 285129 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 15134852 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 449411 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 64885 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 514296 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 4066889 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 4066889 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 4066889 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 449411 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 12940223 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::tsunami.ide 1395205 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 64952 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 284725 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 19202219 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 449493 # Total number of read requests seen
-system.physmem.writeReqs 120791 # Total number of write requests seen
-system.physmem.cpureqs 575904 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 28767552 # Total number of bytes read from memory
-system.physmem.bytesWritten 7730624 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 28767552 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 7730624 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 67 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 5612 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 28381 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 28228 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 28189 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 27984 # Track reads on a per bank basis
+system.physmem.bw_total::cpu1.inst 64885 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 285129 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 19201740 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 449488 # Total number of read requests seen
+system.physmem.writeReqs 120782 # Total number of write requests seen
+system.physmem.cpureqs 575881 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 28767232 # Total number of bytes read from memory
+system.physmem.bytesWritten 7730048 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 28767232 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 7730048 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 76 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 5601 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 28386 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 28227 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::4 28465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 28237 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 28221 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 28024 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 28096 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 28042 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::8 28087 # Track reads on a per bank basis
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system.physmem.perBankRdReqs::10 28071 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 27942 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 27828 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 28001 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 27865 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 27852 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 7819 # Track writes on a per bank basis
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-system.physmem.perBankWrReqs::3 7520 # Track writes on a per bank basis
+system.physmem.perBankRdReqs::11 27938 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::13 28000 # Track reads on a per bank basis
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+system.physmem.perBankRdReqs::15 27848 # Track reads on a per bank basis
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+system.physmem.perBankWrReqs::14 7270 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 7347 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 1900722456000 # Total gap between requests
+system.physmem.numWrRetry 10 # Number of times wr buffer was full causing retry
+system.physmem.totGap 1900723138000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 449493 # Categorize read packet sizes
+system.physmem.readPktSize::6 449488 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 120791 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 319839 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 59260 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 32605 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::19 773 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 120782 # Categorize write packet sizes
+system.physmem.rdQLenPdf::0 319759 # What read queue length does an incoming req see
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system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::20 5251 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::22 5251 # What write queue length does an incoming req see
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system.physmem.wrQLenPdf::29 17 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 14 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 12 # What write queue length does an incoming req see
-system.physmem.totQLat 7695436000 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 15487088500 # Sum of mem lat for all requests
-system.physmem.totBusLat 2247130000 # Total cycles spent in databus access
-system.physmem.totBankLat 5544522500 # Total cycles spent in bank access
-system.physmem.avgQLat 17122.81 # Average queueing delay per request
-system.physmem.avgBankLat 12336.90 # Average bank access latency per request
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-system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007307 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::cpu1.data 0.069145 # mshr miss rate for overall accesses
-system.l2c.overall_mshr_miss_rate::total 0.165953 # mshr miss rate for overall accesses
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31345.258756 # average ReadReq mshr miss latency
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-system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 63842.283482 # average ReadReq mshr miss latency
-system.l2c.ReadReq_avg_mshr_miss_latency::total 32783.237008 # average ReadReq mshr miss latency
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-system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10011.435821 # average UpgradeReq mshr miss latency
-system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10052.094914 # average UpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10022.405357 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_mshr_miss_rate::total 0.400956 # mshr miss rate for ReadExReq accesses
+system.l2c.demand_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for demand accesses
+system.l2c.demand_mshr_miss_rate::total 0.165967 # mshr miss rate for demand accesses
+system.l2c.overall_mshr_miss_rate::cpu0.inst 0.016105 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu0.data 0.308891 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.inst 0.007300 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::cpu1.data 0.069220 # mshr miss rate for overall accesses
+system.l2c.overall_mshr_miss_rate::total 0.165967 # mshr miss rate for overall accesses
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 31335.411763 # average ReadReq mshr miss latency
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+system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 61506.550661 # average ReadReq mshr miss latency
+system.l2c.ReadReq_avg_mshr_miss_latency::total 32753.464222 # average ReadReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 10074.820123 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 10042.529940 # average UpgradeReq mshr miss latency
+system.l2c.UpgradeReq_avg_mshr_miss_latency::total 10064.295682 # average UpgradeReq mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu0.data 10035.796429 # average SCUpgradeReq mshr miss latency
system.l2c.SCUpgradeReq_avg_mshr_miss_latency::cpu1.data 10016.330494 # average SCUpgradeReq mshr miss latency
-system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10019.296425 # average SCUpgradeReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53287.125551 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 86630.763679 # average ReadExReq mshr miss latency
-system.l2c.ReadExReq_avg_mshr_miss_latency::total 55426.871956 # average ReadExReq mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency
-system.l2c.demand_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55357.830101 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37726.163529 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 65562.407983 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::cpu1.data 84248.766682 # average overall mshr miss latency
-system.l2c.overall_avg_mshr_miss_latency::total 39409.127820 # average overall mshr miss latency
+system.l2c.SCUpgradeReq_avg_mshr_miss_latency::total 10025.834350 # average SCUpgradeReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 53182.255952 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 89017.938387 # average ReadExReq mshr miss latency
+system.l2c.ReadExReq_avg_mshr_miss_latency::total 55482.280482 # average ReadExReq mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
+system.l2c.demand_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 55351.362799 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu0.data 37688.654091 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 63540.033731 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::cpu1.data 86108.172510 # average overall mshr miss latency
+system.l2c.overall_avg_mshr_miss_latency::total 39404.227536 # average overall mshr miss latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.l2c.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.l2c.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate
system.iocache.replacements 41699 # number of replacements
-system.iocache.tagsinuse 0.509415 # Cycle average of tags in use
+system.iocache.tagsinuse 0.509421 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
system.iocache.sampled_refs 41715 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
system.iocache.warmup_cycle 1705456216000 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::tsunami.ide 0.509415 # Average occupied blocks per requestor
-system.iocache.occ_percent::tsunami.ide 0.031838 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.031838 # Average percentage of cache occupancy
+system.iocache.occ_blocks::tsunami.ide 0.509421 # Average occupied blocks per requestor
+system.iocache.occ_percent::tsunami.ide 0.031839 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.031839 # Average percentage of cache occupancy
system.iocache.ReadReq_misses::tsunami.ide 179 # number of ReadReq misses
system.iocache.ReadReq_misses::total 179 # number of ReadReq misses
system.iocache.WriteReq_misses::tsunami.ide 41552 # number of WriteReq misses
system.iocache.demand_misses::total 41731 # number of demand (read+write) misses
system.iocache.overall_misses::tsunami.ide 41731 # number of overall misses
system.iocache.overall_misses::total 41731 # number of overall misses
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-system.iocache.ReadReq_miss_latency::total 21612998 # number of ReadReq miss cycles
-system.iocache.WriteReq_miss_latency::tsunami.ide 10624659943 # number of WriteReq miss cycles
-system.iocache.WriteReq_miss_latency::total 10624659943 # number of WriteReq miss cycles
-system.iocache.demand_miss_latency::tsunami.ide 10646272941 # number of demand (read+write) miss cycles
-system.iocache.demand_miss_latency::total 10646272941 # number of demand (read+write) miss cycles
-system.iocache.overall_miss_latency::tsunami.ide 10646272941 # number of overall miss cycles
-system.iocache.overall_miss_latency::total 10646272941 # number of overall miss cycles
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+system.iocache.ReadReq_miss_latency::total 21615998 # number of ReadReq miss cycles
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+system.iocache.WriteReq_miss_latency::total 10647231164 # number of WriteReq miss cycles
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+system.iocache.demand_miss_latency::total 10668847162 # number of demand (read+write) miss cycles
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+system.iocache.overall_miss_latency::total 10668847162 # number of overall miss cycles
system.iocache.ReadReq_accesses::tsunami.ide 179 # number of ReadReq accesses(hits+misses)
system.iocache.ReadReq_accesses::total 179 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::tsunami.ide 41552 # number of WriteReq accesses(hits+misses)
system.iocache.demand_miss_rate::total 1 # miss rate for demand accesses
system.iocache.overall_miss_rate::tsunami.ide 1 # miss rate for overall accesses
system.iocache.overall_miss_rate::total 1 # miss rate for overall accesses
-system.iocache.ReadReq_avg_miss_latency::tsunami.ide 120743.005587 # average ReadReq miss latency
-system.iocache.ReadReq_avg_miss_latency::total 120743.005587 # average ReadReq miss latency
-system.iocache.WriteReq_avg_miss_latency::tsunami.ide 255695.512683 # average WriteReq miss latency
-system.iocache.WriteReq_avg_miss_latency::total 255695.512683 # average WriteReq miss latency
-system.iocache.demand_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency
-system.iocache.demand_avg_miss_latency::total 255116.650476 # average overall miss latency
-system.iocache.overall_avg_miss_latency::tsunami.ide 255116.650476 # average overall miss latency
-system.iocache.overall_avg_miss_latency::total 255116.650476 # average overall miss latency
-system.iocache.blocked_cycles::no_mshrs 284705 # number of cycles access was blocked
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+system.iocache.ReadReq_avg_miss_latency::total 120759.765363 # average ReadReq miss latency
+system.iocache.WriteReq_avg_miss_latency::tsunami.ide 256238.716885 # average WriteReq miss latency
+system.iocache.WriteReq_avg_miss_latency::total 256238.716885 # average WriteReq miss latency
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+system.iocache.demand_avg_miss_latency::total 255657.596559 # average overall miss latency
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+system.iocache.overall_avg_miss_latency::total 255657.596559 # average overall miss latency
+system.iocache.blocked_cycles::no_mshrs 286486 # number of cycles access was blocked
system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.iocache.blocked::no_mshrs 27170 # number of cycles access was blocked
+system.iocache.blocked::no_mshrs 27218 # number of cycles access was blocked
system.iocache.blocked::no_targets 0 # number of cycles access was blocked
-system.iocache.avg_blocked_cycles::no_mshrs 10.478653 # average number of cycles each access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.demand_mshr_misses::total 41731 # number of demand (read+write) MSHR misses
system.iocache.overall_mshr_misses::tsunami.ide 41731 # number of overall MSHR misses
system.iocache.overall_mshr_misses::total 41731 # number of overall MSHR misses
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-system.iocache.ReadReq_mshr_miss_latency::total 12304249 # number of ReadReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::tsunami.ide 8462672446 # number of WriteReq MSHR miss cycles
-system.iocache.WriteReq_mshr_miss_latency::total 8462672446 # number of WriteReq MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::tsunami.ide 8474976695 # number of demand (read+write) MSHR miss cycles
-system.iocache.demand_mshr_miss_latency::total 8474976695 # number of demand (read+write) MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::tsunami.ide 8474976695 # number of overall MSHR miss cycles
-system.iocache.overall_mshr_miss_latency::total 8474976695 # number of overall MSHR miss cycles
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+system.iocache.ReadReq_mshr_miss_latency::total 12307249 # number of ReadReq MSHR miss cycles
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+system.iocache.demand_mshr_miss_latency::total 8497546916 # number of demand (read+write) MSHR miss cycles
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system.iocache.ReadReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for ReadReq accesses
system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
system.iocache.WriteReq_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for WriteReq accesses
system.iocache.demand_mshr_miss_rate::total 1 # mshr miss rate for demand accesses
system.iocache.overall_mshr_miss_rate::tsunami.ide 1 # mshr miss rate for overall accesses
system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
-system.iocache.ReadReq_avg_mshr_miss_latency::tsunami.ide 68738.821229 # average ReadReq mshr miss latency
-system.iocache.ReadReq_avg_mshr_miss_latency::total 68738.821229 # average ReadReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::tsunami.ide 203664.623749 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 203664.623749 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203085.876087 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 203085.876087 # average overall mshr miss latency
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+system.iocache.ReadReq_avg_mshr_miss_latency::total 68755.581006 # average ReadReq mshr miss latency
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+system.iocache.WriteReq_avg_mshr_miss_latency::total 204207.731686 # average WriteReq mshr miss latency
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+system.iocache.demand_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::tsunami.ide 203626.726319 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 203626.726319 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD).
system.disk2.dma_write_full_pages 1 # Number of full page size DMA writes.
system.disk2.dma_write_bytes 8192 # Number of bytes transfered via DMA writes.
system.disk2.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu0.branchPred.lookups 12043910 # Number of BP lookups
-system.cpu0.branchPred.condPredicted 10154859 # Number of conditional branches predicted
-system.cpu0.branchPred.condIncorrect 320144 # Number of conditional branches incorrect
-system.cpu0.branchPred.BTBLookups 7755165 # Number of BTB lookups
-system.cpu0.branchPred.BTBHits 5137994 # Number of BTB hits
+system.cpu0.branchPred.lookups 12035820 # Number of BP lookups
+system.cpu0.branchPred.condPredicted 10146181 # Number of conditional branches predicted
+system.cpu0.branchPred.condIncorrect 320311 # Number of conditional branches incorrect
+system.cpu0.branchPred.BTBLookups 7799891 # Number of BTB lookups
+system.cpu0.branchPred.BTBHits 5138186 # Number of BTB hits
system.cpu0.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu0.branchPred.BTBHitPct 66.252543 # BTB Hit Percentage
-system.cpu0.branchPred.usedRAS 760181 # Number of times the RAS was used to get a target.
-system.cpu0.branchPred.RASInCorrect 30092 # Number of incorrect RAS predictions.
+system.cpu0.branchPred.BTBHitPct 65.875100 # BTB Hit Percentage
+system.cpu0.branchPred.usedRAS 760204 # Number of times the RAS was used to get a target.
+system.cpu0.branchPred.RASInCorrect 30176 # Number of incorrect RAS predictions.
system.cpu0.dtb.fetch_hits 0 # ITB hits
system.cpu0.dtb.fetch_misses 0 # ITB misses
system.cpu0.dtb.fetch_acv 0 # ITB acv
system.cpu0.dtb.fetch_accesses 0 # ITB accesses
-system.cpu0.dtb.read_hits 8552844 # DTB read hits
-system.cpu0.dtb.read_misses 30306 # DTB read misses
-system.cpu0.dtb.read_acv 545 # DTB read access violations
-system.cpu0.dtb.read_accesses 625084 # DTB read accesses
-system.cpu0.dtb.write_hits 5600708 # DTB write hits
-system.cpu0.dtb.write_misses 7703 # DTB write misses
-system.cpu0.dtb.write_acv 337 # DTB write access violations
-system.cpu0.dtb.write_accesses 207517 # DTB write accesses
-system.cpu0.dtb.data_hits 14153552 # DTB hits
-system.cpu0.dtb.data_misses 38009 # DTB misses
-system.cpu0.dtb.data_acv 882 # DTB access violations
-system.cpu0.dtb.data_accesses 832601 # DTB accesses
-system.cpu0.itb.fetch_hits 972187 # ITB hits
-system.cpu0.itb.fetch_misses 27447 # ITB misses
-system.cpu0.itb.fetch_acv 929 # ITB acv
-system.cpu0.itb.fetch_accesses 999634 # ITB accesses
+system.cpu0.dtb.read_hits 8551483 # DTB read hits
+system.cpu0.dtb.read_misses 30199 # DTB read misses
+system.cpu0.dtb.read_acv 541 # DTB read access violations
+system.cpu0.dtb.read_accesses 624803 # DTB read accesses
+system.cpu0.dtb.write_hits 5601236 # DTB write hits
+system.cpu0.dtb.write_misses 7972 # DTB write misses
+system.cpu0.dtb.write_acv 345 # DTB write access violations
+system.cpu0.dtb.write_accesses 208308 # DTB write accesses
+system.cpu0.dtb.data_hits 14152719 # DTB hits
+system.cpu0.dtb.data_misses 38171 # DTB misses
+system.cpu0.dtb.data_acv 886 # DTB access violations
+system.cpu0.dtb.data_accesses 833111 # DTB accesses
+system.cpu0.itb.fetch_hits 970030 # ITB hits
+system.cpu0.itb.fetch_misses 28776 # ITB misses
+system.cpu0.itb.fetch_acv 920 # ITB acv
+system.cpu0.itb.fetch_accesses 998806 # ITB accesses
system.cpu0.itb.read_hits 0 # DTB read hits
system.cpu0.itb.read_misses 0 # DTB read misses
system.cpu0.itb.read_acv 0 # DTB read access violations
system.cpu0.itb.data_misses 0 # DTB misses
system.cpu0.itb.data_acv 0 # DTB access violations
system.cpu0.itb.data_accesses 0 # DTB accesses
-system.cpu0.numCycles 100158206 # number of cpu cycles simulated
+system.cpu0.numCycles 100119117 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.fetch.icacheStallCycles 24091830 # Number of cycles fetch is stalled on an Icache miss
-system.cpu0.fetch.Insts 61851140 # Number of instructions fetch has processed
-system.cpu0.fetch.Branches 12043910 # Number of branches that fetch encountered
-system.cpu0.fetch.predictedBranches 5898175 # Number of branches that fetch has predicted taken
-system.cpu0.fetch.Cycles 11655326 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu0.fetch.SquashCycles 1636923 # Number of cycles fetch has spent squashing
-system.cpu0.fetch.BlockedCycles 36054530 # Number of cycles fetch has spent blocked
-system.cpu0.fetch.MiscStallCycles 31633 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu0.fetch.PendingTrapStallCycles 195301 # Number of stall cycles due to pending traps
-system.cpu0.fetch.PendingQuiesceStallCycles 286219 # Number of stall cycles due to pending quiesce instructions
-system.cpu0.fetch.IcacheWaitRetryStallCycles 317 # Number of stall cycles due to full MSHR
-system.cpu0.fetch.CacheLines 7501974 # Number of cache lines fetched
-system.cpu0.fetch.IcacheSquashes 215877 # Number of outstanding Icache misses that were squashed
-system.cpu0.fetch.rateDist::samples 73371591 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::mean 0.842985 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::stdev 2.179628 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.icacheStallCycles 24086973 # Number of cycles fetch is stalled on an Icache miss
+system.cpu0.fetch.Insts 61837518 # Number of instructions fetch has processed
+system.cpu0.fetch.Branches 12035820 # Number of branches that fetch encountered
+system.cpu0.fetch.predictedBranches 5898390 # Number of branches that fetch has predicted taken
+system.cpu0.fetch.Cycles 11653378 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu0.fetch.SquashCycles 1636628 # Number of cycles fetch has spent squashing
+system.cpu0.fetch.BlockedCycles 36048574 # Number of cycles fetch has spent blocked
+system.cpu0.fetch.MiscStallCycles 32004 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu0.fetch.PendingTrapStallCycles 195358 # Number of stall cycles due to pending traps
+system.cpu0.fetch.PendingQuiesceStallCycles 286105 # Number of stall cycles due to pending quiesce instructions
+system.cpu0.fetch.IcacheWaitRetryStallCycles 287 # Number of stall cycles due to full MSHR
+system.cpu0.fetch.CacheLines 7499654 # Number of cache lines fetched
+system.cpu0.fetch.IcacheSquashes 215735 # Number of outstanding Icache misses that were squashed
+system.cpu0.fetch.rateDist::samples 73358875 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::mean 0.842945 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::stdev 2.179502 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::0 61716265 84.11% 84.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::1 747527 1.02% 85.13% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::2 1537071 2.09% 87.23% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::3 679895 0.93% 88.16% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::4 2532643 3.45% 91.61% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::5 504962 0.69% 92.30% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::6 557623 0.76% 93.06% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::7 776174 1.06% 94.11% # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::8 4319431 5.89% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::0 61705497 84.11% 84.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::1 747609 1.02% 85.13% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::2 1536097 2.09% 87.23% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::3 679694 0.93% 88.15% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::4 2532720 3.45% 91.61% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::5 506441 0.69% 92.30% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::6 557934 0.76% 93.06% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::7 775120 1.06% 94.11% # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.rateDist::8 4317763 5.89% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.rateDist::total 73371591 # Number of instructions fetched each cycle (Total)
-system.cpu0.fetch.branchRate 0.120249 # Number of branch fetches per cycle
-system.cpu0.fetch.rate 0.617534 # Number of inst fetches per cycle
-system.cpu0.decode.IdleCycles 25319035 # Number of cycles decode is idle
-system.cpu0.decode.BlockedCycles 35526581 # Number of cycles decode is blocked
-system.cpu0.decode.RunCycles 10596329 # Number of cycles decode is running
-system.cpu0.decode.UnblockCycles 906729 # Number of cycles decode is unblocking
-system.cpu0.decode.SquashCycles 1022916 # Number of cycles decode is squashing
-system.cpu0.decode.BranchResolved 497694 # Number of times decode resolved a branch
-system.cpu0.decode.BranchMispred 33826 # Number of times decode detected a branch misprediction
-system.cpu0.decode.DecodedInsts 60727079 # Number of instructions handled by decode
-system.cpu0.decode.SquashedInsts 100309 # Number of squashed instructions handled by decode
-system.cpu0.rename.SquashCycles 1022916 # Number of cycles rename is squashing
-system.cpu0.rename.IdleCycles 26298028 # Number of cycles rename is idle
-system.cpu0.rename.BlockCycles 14528907 # Number of cycles rename is blocking
-system.cpu0.rename.serializeStallCycles 17589039 # count of cycles rename stalled for serializing inst
-system.cpu0.rename.RunCycles 9932796 # Number of cycles rename is running
-system.cpu0.rename.UnblockCycles 3999903 # Number of cycles rename is unblocking
-system.cpu0.rename.RenamedInsts 57523389 # Number of instructions processed by rename
-system.cpu0.rename.ROBFullEvents 6753 # Number of times rename has blocked due to ROB full
-system.cpu0.rename.IQFullEvents 634761 # Number of times rename has blocked due to IQ full
-system.cpu0.rename.LSQFullEvents 1396221 # Number of times rename has blocked due to LSQ full
-system.cpu0.rename.RenamedOperands 38578819 # Number of destination operands rename has renamed
-system.cpu0.rename.RenameLookups 70143462 # Number of register rename lookups that rename has made
-system.cpu0.rename.int_rename_lookups 69780146 # Number of integer rename lookups
-system.cpu0.rename.fp_rename_lookups 363316 # Number of floating rename lookups
-system.cpu0.rename.CommittedMaps 33936686 # Number of HB maps that are committed
-system.cpu0.rename.UndoneMaps 4642125 # Number of HB maps that are undone due to squashing
-system.cpu0.rename.serializingInsts 1392017 # count of serializing insts renamed
-system.cpu0.rename.tempSerializingInsts 201999 # count of temporary serializing insts renamed
-system.cpu0.rename.skidInsts 10851427 # count of insts added to the skid buffer
-system.cpu0.memDep0.insertedLoads 8946001 # Number of loads inserted to the mem dependence unit.
-system.cpu0.memDep0.insertedStores 5847624 # Number of stores inserted to the mem dependence unit.
-system.cpu0.memDep0.conflictingLoads 1117431 # Number of conflicting loads.
-system.cpu0.memDep0.conflictingStores 730012 # Number of conflicting stores.
-system.cpu0.iq.iqInstsAdded 51082073 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu0.iq.iqNonSpecInstsAdded 1726481 # Number of non-speculative instructions added to the IQ
-system.cpu0.iq.iqInstsIssued 49977399 # Number of instructions issued
-system.cpu0.iq.iqSquashedInstsIssued 73178 # Number of squashed instructions issued
-system.cpu0.iq.iqSquashedInstsExamined 5678222 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu0.iq.iqSquashedOperandsExamined 2880000 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu0.iq.iqSquashedNonSpecRemoved 1168367 # Number of squashed non-spec instructions that were removed
-system.cpu0.iq.issued_per_cycle::samples 73371591 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::mean 0.681155 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::stdev 1.330222 # Number of insts issued each cycle
+system.cpu0.fetch.rateDist::total 73358875 # Number of instructions fetched each cycle (Total)
+system.cpu0.fetch.branchRate 0.120215 # Number of branch fetches per cycle
+system.cpu0.fetch.rate 0.617639 # Number of inst fetches per cycle
+system.cpu0.decode.IdleCycles 25314409 # Number of cycles decode is idle
+system.cpu0.decode.BlockedCycles 35520182 # Number of cycles decode is blocked
+system.cpu0.decode.RunCycles 10594612 # Number of cycles decode is running
+system.cpu0.decode.UnblockCycles 907065 # Number of cycles decode is unblocking
+system.cpu0.decode.SquashCycles 1022606 # Number of cycles decode is squashing
+system.cpu0.decode.BranchResolved 498090 # Number of times decode resolved a branch
+system.cpu0.decode.BranchMispred 33900 # Number of times decode detected a branch misprediction
+system.cpu0.decode.DecodedInsts 60717129 # Number of instructions handled by decode
+system.cpu0.decode.SquashedInsts 100549 # Number of squashed instructions handled by decode
+system.cpu0.rename.SquashCycles 1022606 # Number of cycles rename is squashing
+system.cpu0.rename.IdleCycles 26293542 # Number of cycles rename is idle
+system.cpu0.rename.BlockCycles 14517617 # Number of cycles rename is blocking
+system.cpu0.rename.serializeStallCycles 17593984 # count of cycles rename stalled for serializing inst
+system.cpu0.rename.RunCycles 9931348 # Number of cycles rename is running
+system.cpu0.rename.UnblockCycles 3999776 # Number of cycles rename is unblocking
+system.cpu0.rename.RenamedInsts 57516764 # Number of instructions processed by rename
+system.cpu0.rename.ROBFullEvents 6773 # Number of times rename has blocked due to ROB full
+system.cpu0.rename.IQFullEvents 634732 # Number of times rename has blocked due to IQ full
+system.cpu0.rename.LSQFullEvents 1395914 # Number of times rename has blocked due to LSQ full
+system.cpu0.rename.RenamedOperands 38573698 # Number of destination operands rename has renamed
+system.cpu0.rename.RenameLookups 70135572 # Number of register rename lookups that rename has made
+system.cpu0.rename.int_rename_lookups 69772127 # Number of integer rename lookups
+system.cpu0.rename.fp_rename_lookups 363445 # Number of floating rename lookups
+system.cpu0.rename.CommittedMaps 33935332 # Number of HB maps that are committed
+system.cpu0.rename.UndoneMaps 4638358 # Number of HB maps that are undone due to squashing
+system.cpu0.rename.serializingInsts 1391962 # count of serializing insts renamed
+system.cpu0.rename.tempSerializingInsts 201915 # count of temporary serializing insts renamed
+system.cpu0.rename.skidInsts 10849961 # count of insts added to the skid buffer
+system.cpu0.memDep0.insertedLoads 8944130 # Number of loads inserted to the mem dependence unit.
+system.cpu0.memDep0.insertedStores 5848227 # Number of stores inserted to the mem dependence unit.
+system.cpu0.memDep0.conflictingLoads 1106835 # Number of conflicting loads.
+system.cpu0.memDep0.conflictingStores 734658 # Number of conflicting stores.
+system.cpu0.iq.iqInstsAdded 51076458 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu0.iq.iqNonSpecInstsAdded 1725873 # Number of non-speculative instructions added to the IQ
+system.cpu0.iq.iqInstsIssued 49974476 # Number of instructions issued
+system.cpu0.iq.iqSquashedInstsIssued 73247 # Number of squashed instructions issued
+system.cpu0.iq.iqSquashedInstsExamined 5675710 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu0.iq.iqSquashedOperandsExamined 2876244 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu0.iq.iqSquashedNonSpecRemoved 1167818 # Number of squashed non-spec instructions that were removed
+system.cpu0.iq.issued_per_cycle::samples 73358875 # Number of insts issued each cycle
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system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::0 51161805 69.73% 69.73% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::1 10104192 13.77% 83.50% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::2 4556124 6.21% 89.71% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::3 2996769 4.08% 93.80% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::4 2381620 3.25% 97.04% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::5 1186935 1.62% 98.66% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::6 631731 0.86% 99.52% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::7 300209 0.41% 99.93% # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::8 52206 0.07% 100.00% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::0 51151747 69.73% 69.73% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::1 10102031 13.77% 83.50% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::2 4555933 6.21% 89.71% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::3 2996125 4.08% 93.79% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::4 2381484 3.25% 97.04% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::5 1187378 1.62% 98.66% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::6 631915 0.86% 99.52% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::7 300208 0.41% 99.93% # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::8 52054 0.07% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu0.iq.issued_per_cycle::total 73371591 # Number of insts issued each cycle
+system.cpu0.iq.issued_per_cycle::total 73358875 # Number of insts issued each cycle
system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntAlu 82861 12.68% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.68% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemRead 300856 46.05% 58.73% # attempts to use FU when none available
-system.cpu0.iq.fu_full::MemWrite 269656 41.27% 100.00% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntAlu 82701 12.59% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::IntDiv 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatAdd 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatDiv 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAdd 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdAlu 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMisc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShift 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 12.59% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemRead 300975 45.82% 58.41% # attempts to use FU when none available
+system.cpu0.iq.fu_full::MemWrite 273171 41.59% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu0.iq.FU_type_0::No_OpClass 3774 0.01% 0.01% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntAlu 34556272 69.14% 69.15% # Type of FU issued
-system.cpu0.iq.FU_type_0::IntMult 54837 0.11% 69.26% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntAlu 34554089 69.14% 69.15% # Type of FU issued
+system.cpu0.iq.FU_type_0::IntMult 54830 0.11% 69.26% # Type of FU issued
system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 69.26% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatAdd 15268 0.03% 69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 69.29% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 69.30% # Type of FU issued
system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 69.30% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemRead 8895592 17.80% 87.09% # Type of FU issued
-system.cpu0.iq.FU_type_0::MemWrite 5666859 11.34% 98.43% # Type of FU issued
-system.cpu0.iq.FU_type_0::IprAccess 782918 1.57% 100.00% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemRead 8894109 17.80% 87.09% # Type of FU issued
+system.cpu0.iq.FU_type_0::MemWrite 5667707 11.34% 98.43% # Type of FU issued
+system.cpu0.iq.FU_type_0::IprAccess 782820 1.57% 100.00% # Type of FU issued
system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu0.iq.FU_type_0::total 49977399 # Type of FU issued
-system.cpu0.iq.rate 0.498985 # Inst issue rate
-system.cpu0.iq.fu_busy_cnt 653373 # FU busy when requested
-system.cpu0.iq.fu_busy_rate 0.013073 # FU busy rate (busy events/executed inst)
-system.cpu0.iq.int_inst_queue_reads 173532405 # Number of integer instruction queue reads
-system.cpu0.iq.int_inst_queue_writes 58247054 # Number of integer instruction queue writes
-system.cpu0.iq.int_inst_queue_wakeup_accesses 48998129 # Number of integer instruction queue wakeup accesses
-system.cpu0.iq.fp_inst_queue_reads 520534 # Number of floating instruction queue reads
-system.cpu0.iq.fp_inst_queue_writes 252057 # Number of floating instruction queue writes
-system.cpu0.iq.fp_inst_queue_wakeup_accesses 245907 # Number of floating instruction queue wakeup accesses
-system.cpu0.iq.int_alu_accesses 50354702 # Number of integer alu accesses
-system.cpu0.iq.fp_alu_accesses 272296 # Number of floating point alu accesses
-system.cpu0.iew.lsq.thread0.forwLoads 532613 # Number of loads that had data forwarded from stores
+system.cpu0.iq.FU_type_0::total 49974476 # Type of FU issued
+system.cpu0.iq.rate 0.499150 # Inst issue rate
+system.cpu0.iq.fu_busy_cnt 656847 # FU busy when requested
+system.cpu0.iq.fu_busy_rate 0.013144 # FU busy rate (busy events/executed inst)
+system.cpu0.iq.int_inst_queue_reads 173517181 # Number of integer instruction queue reads
+system.cpu0.iq.int_inst_queue_writes 58238103 # Number of integer instruction queue writes
+system.cpu0.iq.int_inst_queue_wakeup_accesses 48994356 # Number of integer instruction queue wakeup accesses
+system.cpu0.iq.fp_inst_queue_reads 520739 # Number of floating instruction queue reads
+system.cpu0.iq.fp_inst_queue_writes 252277 # Number of floating instruction queue writes
+system.cpu0.iq.fp_inst_queue_wakeup_accesses 246003 # Number of floating instruction queue wakeup accesses
+system.cpu0.iq.int_alu_accesses 50355146 # Number of integer alu accesses
+system.cpu0.iq.fp_alu_accesses 272403 # Number of floating point alu accesses
+system.cpu0.iew.lsq.thread0.forwLoads 532794 # Number of loads that had data forwarded from stores
system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu0.iew.lsq.thread0.squashedLoads 1057319 # Number of loads squashed
-system.cpu0.iew.lsq.thread0.ignoredResponses 3456 # Number of memory responses ignored because the instruction is squashed
-system.cpu0.iew.lsq.thread0.memOrderViolation 12575 # Number of memory ordering violations
-system.cpu0.iew.lsq.thread0.squashedStores 434127 # Number of stores squashed
+system.cpu0.iew.lsq.thread0.squashedLoads 1055829 # Number of loads squashed
+system.cpu0.iew.lsq.thread0.ignoredResponses 3465 # Number of memory responses ignored because the instruction is squashed
+system.cpu0.iew.lsq.thread0.memOrderViolation 12581 # Number of memory ordering violations
+system.cpu0.iew.lsq.thread0.squashedStores 434891 # Number of stores squashed
system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu0.iew.lsq.thread0.rescheduledLoads 18424 # Number of loads that were rescheduled
-system.cpu0.iew.lsq.thread0.cacheBlocked 121082 # Number of times an access to memory failed due to the cache being blocked
+system.cpu0.iew.lsq.thread0.rescheduledLoads 18411 # Number of loads that were rescheduled
+system.cpu0.iew.lsq.thread0.cacheBlocked 121190 # Number of times an access to memory failed due to the cache being blocked
system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu0.iew.iewSquashCycles 1022916 # Number of cycles IEW is squashing
-system.cpu0.iew.iewBlockCycles 10363943 # Number of cycles IEW is blocking
-system.cpu0.iew.iewUnblockCycles 778495 # Number of cycles IEW is unblocking
-system.cpu0.iew.iewDispatchedInsts 55942043 # Number of instructions dispatched to IQ
-system.cpu0.iew.iewDispSquashedInsts 586758 # Number of squashed instructions skipped by dispatch
-system.cpu0.iew.iewDispLoadInsts 8946001 # Number of dispatched load instructions
-system.cpu0.iew.iewDispStoreInsts 5847624 # Number of dispatched store instructions
-system.cpu0.iew.iewDispNonSpecInsts 1520655 # Number of dispatched non-speculative instructions
-system.cpu0.iew.iewIQFullEvents 566622 # Number of times the IQ has become full, causing a stall
-system.cpu0.iew.iewLSQFullEvents 4762 # Number of times the LSQ has become full, causing a stall
-system.cpu0.iew.memOrderViolationEvents 12575 # Number of memory order violations
-system.cpu0.iew.predictedTakenIncorrect 160322 # Number of branches that were predicted taken incorrectly
-system.cpu0.iew.predictedNotTakenIncorrect 334940 # Number of branches that were predicted not taken incorrectly
-system.cpu0.iew.branchMispredicts 495262 # Number of branch mispredicts detected at execute
-system.cpu0.iew.iewExecutedInsts 49600607 # Number of executed instructions
-system.cpu0.iew.iewExecLoadInsts 8605587 # Number of load instructions executed
-system.cpu0.iew.iewExecSquashedInsts 376791 # Number of squashed instructions skipped in execute
+system.cpu0.iew.iewSquashCycles 1022606 # Number of cycles IEW is squashing
+system.cpu0.iew.iewBlockCycles 10355478 # Number of cycles IEW is blocking
+system.cpu0.iew.iewUnblockCycles 778603 # Number of cycles IEW is unblocking
+system.cpu0.iew.iewDispatchedInsts 55935625 # Number of instructions dispatched to IQ
+system.cpu0.iew.iewDispSquashedInsts 586886 # Number of squashed instructions skipped by dispatch
+system.cpu0.iew.iewDispLoadInsts 8944130 # Number of dispatched load instructions
+system.cpu0.iew.iewDispStoreInsts 5848227 # Number of dispatched store instructions
+system.cpu0.iew.iewDispNonSpecInsts 1520110 # Number of dispatched non-speculative instructions
+system.cpu0.iew.iewIQFullEvents 566642 # Number of times the IQ has become full, causing a stall
+system.cpu0.iew.iewLSQFullEvents 4768 # Number of times the LSQ has become full, causing a stall
+system.cpu0.iew.memOrderViolationEvents 12581 # Number of memory order violations
+system.cpu0.iew.predictedTakenIncorrect 160372 # Number of branches that were predicted taken incorrectly
+system.cpu0.iew.predictedNotTakenIncorrect 334885 # Number of branches that were predicted not taken incorrectly
+system.cpu0.iew.branchMispredicts 495257 # Number of branch mispredicts detected at execute
+system.cpu0.iew.iewExecutedInsts 49597141 # Number of executed instructions
+system.cpu0.iew.iewExecLoadInsts 8604090 # Number of load instructions executed
+system.cpu0.iew.iewExecSquashedInsts 377334 # Number of squashed instructions skipped in execute
system.cpu0.iew.exec_swp 0 # number of swp insts executed
-system.cpu0.iew.exec_nop 3133489 # number of nop insts executed
-system.cpu0.iew.exec_refs 14227227 # number of memory reference insts executed
-system.cpu0.iew.exec_branches 7905275 # Number of branches executed
-system.cpu0.iew.exec_stores 5621640 # Number of stores executed
-system.cpu0.iew.exec_rate 0.495223 # Inst execution rate
-system.cpu0.iew.wb_sent 49330113 # cumulative count of insts sent to commit
-system.cpu0.iew.wb_count 49244036 # cumulative count of insts written-back
-system.cpu0.iew.wb_producers 24627791 # num instructions producing a value
-system.cpu0.iew.wb_consumers 33147398 # num instructions consuming a value
+system.cpu0.iew.exec_nop 3133294 # number of nop insts executed
+system.cpu0.iew.exec_refs 14226525 # number of memory reference insts executed
+system.cpu0.iew.exec_branches 7904799 # Number of branches executed
+system.cpu0.iew.exec_stores 5622435 # Number of stores executed
+system.cpu0.iew.exec_rate 0.495381 # Inst execution rate
+system.cpu0.iew.wb_sent 49326582 # cumulative count of insts sent to commit
+system.cpu0.iew.wb_count 49240359 # cumulative count of insts written-back
+system.cpu0.iew.wb_producers 24624844 # num instructions producing a value
+system.cpu0.iew.wb_consumers 33143444 # num instructions consuming a value
system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu0.iew.wb_rate 0.491663 # insts written-back per cycle
+system.cpu0.iew.wb_rate 0.491818 # insts written-back per cycle
system.cpu0.iew.wb_fanout 0.742978 # average fanout of values written-back
system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu0.commit.commitSquashedInsts 6114712 # The number of squashed insts skipped by commit
-system.cpu0.commit.commitNonSpecStalls 558114 # The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.branchMispredicts 462555 # The number of times a branch was mispredicted
-system.cpu0.commit.committed_per_cycle::samples 72348675 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::mean 0.687235 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::stdev 1.603400 # Number of insts commited each cycle
+system.cpu0.commit.commitSquashedInsts 6108836 # The number of squashed insts skipped by commit
+system.cpu0.commit.commitNonSpecStalls 558055 # The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.branchMispredicts 462633 # The number of times a branch was mispredicted
+system.cpu0.commit.committed_per_cycle::samples 72336269 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::mean 0.687326 # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::stdev 1.603373 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::0 53652549 74.16% 74.16% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::1 7790867 10.77% 84.93% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::2 4280150 5.92% 90.84% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::3 2308289 3.19% 94.03% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::4 1285405 1.78% 95.81% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::5 537706 0.74% 96.55% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::6 453758 0.63% 97.18% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::7 427812 0.59% 97.77% # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::8 1612139 2.23% 100.00% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::0 53637775 74.15% 74.15% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::1 7794815 10.78% 84.93% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::2 4279099 5.92% 90.84% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::3 2307939 3.19% 94.03% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::4 1284633 1.78% 95.81% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::5 537599 0.74% 96.55% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::6 458507 0.63% 97.19% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::7 423032 0.58% 97.77% # Number of insts commited each cycle
+system.cpu0.commit.committed_per_cycle::8 1612870 2.23% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu0.commit.committed_per_cycle::total 72348675 # Number of insts commited each cycle
-system.cpu0.commit.committedInsts 49720528 # Number of instructions committed
-system.cpu0.commit.committedOps 49720528 # Number of ops (including micro ops) committed
+system.cpu0.commit.committed_per_cycle::total 72336269 # Number of insts commited each cycle
+system.cpu0.commit.committedInsts 49718583 # Number of instructions committed
+system.cpu0.commit.committedOps 49718583 # Number of ops (including micro ops) committed
system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu0.commit.refs 13302179 # Number of memory references committed
-system.cpu0.commit.loads 7888682 # Number of loads committed
-system.cpu0.commit.membars 189617 # Number of memory barriers committed
-system.cpu0.commit.branches 7516247 # Number of branches committed
+system.cpu0.commit.refs 13301637 # Number of memory references committed
+system.cpu0.commit.loads 7888301 # Number of loads committed
+system.cpu0.commit.membars 189589 # Number of memory barriers committed
+system.cpu0.commit.branches 7515884 # Number of branches committed
system.cpu0.commit.fp_insts 243820 # Number of committed floating point instructions.
-system.cpu0.commit.int_insts 46057183 # Number of committed integer instructions.
-system.cpu0.commit.function_calls 629253 # Number of function calls committed.
-system.cpu0.commit.bw_lim_events 1612139 # number cycles where commit BW limit reached
+system.cpu0.commit.int_insts 46055357 # Number of committed integer instructions.
+system.cpu0.commit.function_calls 629203 # Number of function calls committed.
+system.cpu0.commit.bw_lim_events 1612870 # number cycles where commit BW limit reached
system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu0.rob.rob_reads 126376352 # The number of ROB reads
-system.cpu0.rob.rob_writes 112693596 # The number of ROB writes
-system.cpu0.timesIdled 1033507 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu0.idleCycles 26786615 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu0.quiesceCycles 3701289214 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu0.committedInsts 46865102 # Number of Instructions Simulated
-system.cpu0.committedOps 46865102 # Number of Ops (including micro ops) Simulated
-system.cpu0.committedInsts_total 46865102 # Number of Instructions Simulated
-system.cpu0.cpi 2.137160 # CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.137160 # CPI: Total CPI of All Threads
-system.cpu0.ipc 0.467911 # IPC: Instructions Per Cycle
-system.cpu0.ipc_total 0.467911 # IPC: Total IPC of All Threads
-system.cpu0.int_regfile_reads 65365755 # number of integer regfile reads
-system.cpu0.int_regfile_writes 35683177 # number of integer regfile writes
-system.cpu0.fp_regfile_reads 120752 # number of floating regfile reads
-system.cpu0.fp_regfile_writes 122064 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 1632145 # number of misc regfile reads
-system.cpu0.misc_regfile_writes 781535 # number of misc regfile writes
+system.cpu0.rob.rob_reads 126355419 # The number of ROB reads
+system.cpu0.rob.rob_writes 112677687 # The number of ROB writes
+system.cpu0.timesIdled 1033455 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu0.idleCycles 26760242 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu0.quiesceCycles 3701329669 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu0.committedInsts 46863203 # Number of Instructions Simulated
+system.cpu0.committedOps 46863203 # Number of Ops (including micro ops) Simulated
+system.cpu0.committedInsts_total 46863203 # Number of Instructions Simulated
+system.cpu0.cpi 2.136412 # CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.136412 # CPI: Total CPI of All Threads
+system.cpu0.ipc 0.468074 # IPC: Instructions Per Cycle
+system.cpu0.ipc_total 0.468074 # IPC: Total IPC of All Threads
+system.cpu0.int_regfile_reads 65361385 # number of integer regfile reads
+system.cpu0.int_regfile_writes 35679513 # number of integer regfile writes
+system.cpu0.fp_regfile_reads 120846 # number of floating regfile reads
+system.cpu0.fp_regfile_writes 122066 # number of floating regfile writes
+system.cpu0.misc_regfile_reads 1631915 # number of misc regfile reads
+system.cpu0.misc_regfile_writes 781460 # number of misc regfile writes
system.tsunami.ethernet.descDMAReads 0 # Number of descriptors the device read w/ DMA
system.tsunami.ethernet.descDMAWrites 0 # Number of descriptors the device wrote w/ DMA
system.tsunami.ethernet.descDmaReadBytes 0 # number of descriptor bytes read w/ DMA
system.tsunami.ethernet.coalescedTotal nan # average number of interrupts coalesced into each post
system.tsunami.ethernet.postedInterrupts 0 # number of posts to CPU
system.tsunami.ethernet.droppedPackets 0 # number of packets dropped
-system.cpu0.icache.replacements 828572 # number of replacements
-system.cpu0.icache.tagsinuse 510.309366 # Cycle average of tags in use
-system.cpu0.icache.total_refs 6631345 # Total number of references to valid blocks.
-system.cpu0.icache.sampled_refs 829084 # Sample count of references to valid blocks.
-system.cpu0.icache.avg_refs 7.998399 # Average number of references to valid blocks.
+system.cpu0.icache.replacements 828283 # number of replacements
+system.cpu0.icache.tagsinuse 510.309737 # Cycle average of tags in use
+system.cpu0.icache.total_refs 6629306 # Total number of references to valid blocks.
+system.cpu0.icache.sampled_refs 828795 # Sample count of references to valid blocks.
+system.cpu0.icache.avg_refs 7.998728 # Average number of references to valid blocks.
system.cpu0.icache.warmup_cycle 20510250000 # Cycle when the warmup percentage was hit.
-system.cpu0.icache.occ_blocks::cpu0.inst 510.309366 # Average occupied blocks per requestor
-system.cpu0.icache.occ_percent::cpu0.inst 0.996698 # Average percentage of cache occupancy
-system.cpu0.icache.occ_percent::total 0.996698 # Average percentage of cache occupancy
-system.cpu0.icache.ReadReq_hits::cpu0.inst 6631345 # number of ReadReq hits
-system.cpu0.icache.ReadReq_hits::total 6631345 # number of ReadReq hits
-system.cpu0.icache.demand_hits::cpu0.inst 6631345 # number of demand (read+write) hits
-system.cpu0.icache.demand_hits::total 6631345 # number of demand (read+write) hits
-system.cpu0.icache.overall_hits::cpu0.inst 6631345 # number of overall hits
-system.cpu0.icache.overall_hits::total 6631345 # number of overall hits
-system.cpu0.icache.ReadReq_misses::cpu0.inst 870628 # number of ReadReq misses
-system.cpu0.icache.ReadReq_misses::total 870628 # number of ReadReq misses
-system.cpu0.icache.demand_misses::cpu0.inst 870628 # number of demand (read+write) misses
-system.cpu0.icache.demand_misses::total 870628 # number of demand (read+write) misses
-system.cpu0.icache.overall_misses::cpu0.inst 870628 # number of overall misses
-system.cpu0.icache.overall_misses::total 870628 # number of overall misses
-system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12335909994 # number of ReadReq miss cycles
-system.cpu0.icache.ReadReq_miss_latency::total 12335909994 # number of ReadReq miss cycles
-system.cpu0.icache.demand_miss_latency::cpu0.inst 12335909994 # number of demand (read+write) miss cycles
-system.cpu0.icache.demand_miss_latency::total 12335909994 # number of demand (read+write) miss cycles
-system.cpu0.icache.overall_miss_latency::cpu0.inst 12335909994 # number of overall miss cycles
-system.cpu0.icache.overall_miss_latency::total 12335909994 # number of overall miss cycles
-system.cpu0.icache.ReadReq_accesses::cpu0.inst 7501973 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.ReadReq_accesses::total 7501973 # number of ReadReq accesses(hits+misses)
-system.cpu0.icache.demand_accesses::cpu0.inst 7501973 # number of demand (read+write) accesses
-system.cpu0.icache.demand_accesses::total 7501973 # number of demand (read+write) accesses
-system.cpu0.icache.overall_accesses::cpu0.inst 7501973 # number of overall (read+write) accesses
-system.cpu0.icache.overall_accesses::total 7501973 # number of overall (read+write) accesses
-system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116053 # miss rate for ReadReq accesses
-system.cpu0.icache.ReadReq_miss_rate::total 0.116053 # miss rate for ReadReq accesses
-system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116053 # miss rate for demand accesses
-system.cpu0.icache.demand_miss_rate::total 0.116053 # miss rate for demand accesses
-system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116053 # miss rate for overall accesses
-system.cpu0.icache.overall_miss_rate::total 0.116053 # miss rate for overall accesses
-system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14168.979167 # average ReadReq miss latency
-system.cpu0.icache.ReadReq_avg_miss_latency::total 14168.979167 # average ReadReq miss latency
-system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency
-system.cpu0.icache.demand_avg_miss_latency::total 14168.979167 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14168.979167 # average overall miss latency
-system.cpu0.icache.overall_avg_miss_latency::total 14168.979167 # average overall miss latency
-system.cpu0.icache.blocked_cycles::no_mshrs 2773 # number of cycles access was blocked
+system.cpu0.icache.occ_blocks::cpu0.inst 510.309737 # Average occupied blocks per requestor
+system.cpu0.icache.occ_percent::cpu0.inst 0.996699 # Average percentage of cache occupancy
+system.cpu0.icache.occ_percent::total 0.996699 # Average percentage of cache occupancy
+system.cpu0.icache.ReadReq_hits::cpu0.inst 6629306 # number of ReadReq hits
+system.cpu0.icache.ReadReq_hits::total 6629306 # number of ReadReq hits
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+system.cpu0.icache.overall_hits::total 6629306 # number of overall hits
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+system.cpu0.icache.ReadReq_misses::total 870348 # number of ReadReq misses
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+system.cpu0.icache.overall_misses::total 870348 # number of overall misses
+system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 12313538494 # number of ReadReq miss cycles
+system.cpu0.icache.ReadReq_miss_latency::total 12313538494 # number of ReadReq miss cycles
+system.cpu0.icache.demand_miss_latency::cpu0.inst 12313538494 # number of demand (read+write) miss cycles
+system.cpu0.icache.demand_miss_latency::total 12313538494 # number of demand (read+write) miss cycles
+system.cpu0.icache.overall_miss_latency::cpu0.inst 12313538494 # number of overall miss cycles
+system.cpu0.icache.overall_miss_latency::total 12313538494 # number of overall miss cycles
+system.cpu0.icache.ReadReq_accesses::cpu0.inst 7499654 # number of ReadReq accesses(hits+misses)
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+system.cpu0.icache.demand_accesses::total 7499654 # number of demand (read+write) accesses
+system.cpu0.icache.overall_accesses::cpu0.inst 7499654 # number of overall (read+write) accesses
+system.cpu0.icache.overall_accesses::total 7499654 # number of overall (read+write) accesses
+system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.116052 # miss rate for ReadReq accesses
+system.cpu0.icache.ReadReq_miss_rate::total 0.116052 # miss rate for ReadReq accesses
+system.cpu0.icache.demand_miss_rate::cpu0.inst 0.116052 # miss rate for demand accesses
+system.cpu0.icache.demand_miss_rate::total 0.116052 # miss rate for demand accesses
+system.cpu0.icache.overall_miss_rate::cpu0.inst 0.116052 # miss rate for overall accesses
+system.cpu0.icache.overall_miss_rate::total 0.116052 # miss rate for overall accesses
+system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 14147.833388 # average ReadReq miss latency
+system.cpu0.icache.ReadReq_avg_miss_latency::total 14147.833388 # average ReadReq miss latency
+system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
+system.cpu0.icache.demand_avg_miss_latency::total 14147.833388 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 14147.833388 # average overall miss latency
+system.cpu0.icache.overall_avg_miss_latency::total 14147.833388 # average overall miss latency
+system.cpu0.icache.blocked_cycles::no_mshrs 3221 # number of cycles access was blocked
system.cpu0.icache.blocked_cycles::no_targets 1246 # number of cycles access was blocked
-system.cpu0.icache.blocked::no_mshrs 145 # number of cycles access was blocked
+system.cpu0.icache.blocked::no_mshrs 147 # number of cycles access was blocked
system.cpu0.icache.blocked::no_targets 2 # number of cycles access was blocked
-system.cpu0.icache.avg_blocked_cycles::no_mshrs 19.124138 # average number of cycles each access was blocked
+system.cpu0.icache.avg_blocked_cycles::no_mshrs 21.911565 # average number of cycles each access was blocked
system.cpu0.icache.avg_blocked_cycles::no_targets 623 # average number of cycles each access was blocked
system.cpu0.icache.fast_writes 0 # number of fast writes performed
system.cpu0.icache.cache_copies 0 # number of cache copies performed
-system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 41361 # number of ReadReq MSHR hits
-system.cpu0.icache.ReadReq_mshr_hits::total 41361 # number of ReadReq MSHR hits
-system.cpu0.icache.demand_mshr_hits::cpu0.inst 41361 # number of demand (read+write) MSHR hits
-system.cpu0.icache.demand_mshr_hits::total 41361 # number of demand (read+write) MSHR hits
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-system.cpu0.icache.overall_mshr_hits::total 41361 # number of overall MSHR hits
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-system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 10145672495 # number of demand (read+write) MSHR miss cycles
-system.cpu0.icache.demand_mshr_miss_latency::total 10145672495 # number of demand (read+write) MSHR miss cycles
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-system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 12234.506492 # average ReadReq mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency
-system.cpu0.icache.demand_avg_mshr_miss_latency::total 12234.506492 # average overall mshr miss latency
-system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 12234.506492 # average overall mshr miss latency
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-system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7319.351380 # average StoreCondReq miss latency
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-system.cpu0.dcache.demand_avg_miss_latency::total 30407.569986 # average overall miss latency
-system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 30407.569986 # average overall miss latency
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+system.cpu0.dcache.LoadLockedReq_avg_miss_latency::total 14078.387146 # average LoadLockedReq miss latency
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+system.cpu0.dcache.StoreCondReq_avg_miss_latency::total 7321.581769 # average StoreCondReq miss latency
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system.cpu0.dcache.avg_blocked_cycles::no_targets 170.285714 # average number of cycles each access was blocked
system.cpu0.dcache.fast_writes 0 # number of fast writes performed
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-system.cpu0.dcache.WriteReq_mshr_misses::total 265762 # number of WriteReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15421 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15421 # number of LoadLockedReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3731 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.StoreCondReq_mshr_misses::total 3731 # number of StoreCondReq MSHR misses
-system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250440 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.demand_mshr_misses::total 1250440 # number of demand (read+write) MSHR misses
-system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250440 # number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_misses::total 1250440 # number of overall MSHR misses
-system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21285796500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21285796500 # number of ReadReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9471560262 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9471560262 # number of WriteReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170594000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170594000 # number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19846500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19846500 # number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30757356762 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_latency::total 30757356762 # number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30757356762 # number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_latency::total 30757356762 # number of overall MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1454223000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1454223000 # number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2157391999 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2157391999 # number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3611614999 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3611614999 # number of overall MSHR uncacheable cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127000 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127000 # mshr miss rate for ReadReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050939 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050939 # mshr miss rate for WriteReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088498 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088498 # mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020550 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020550 # mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_miss_rate::total 0.096405 # mshr miss rate for demand accesses
-system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096405 # mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_miss_rate::total 0.096405 # mshr miss rate for overall accesses
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21617.012363 # average ReadReq mshr miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21617.012363 # average ReadReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35639.257162 # average WriteReq mshr miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35639.257162 # average WriteReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.447312 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.447312 # average LoadLockedReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5319.351380 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5319.351380 # average StoreCondReq mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24597.227186 # average overall mshr miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24597.227186 # average overall mshr miss latency
+system.cpu0.dcache.writebacks::writebacks 729852 # number of writebacks
+system.cpu0.dcache.writebacks::total 729852 # number of writebacks
+system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 558383 # number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_hits::total 558383 # number of ReadReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1432185 # number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_hits::total 1432185 # number of WriteReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::cpu0.data 4312 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_hits::total 4312 # number of LoadLockedReq MSHR hits
+system.cpu0.dcache.demand_mshr_hits::cpu0.data 1990568 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_hits::total 1990568 # number of demand (read+write) MSHR hits
+system.cpu0.dcache.overall_mshr_hits::cpu0.data 1990568 # number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_hits::total 1990568 # number of overall MSHR hits
+system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 984658 # number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_misses::total 984658 # number of ReadReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 265791 # number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_misses::total 265791 # number of WriteReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::cpu0.data 15417 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.LoadLockedReq_mshr_misses::total 15417 # number of LoadLockedReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::cpu0.data 3730 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.StoreCondReq_mshr_misses::total 3730 # number of StoreCondReq MSHR misses
+system.cpu0.dcache.demand_mshr_misses::cpu0.data 1250449 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_mshr_misses::total 1250449 # number of demand (read+write) MSHR misses
+system.cpu0.dcache.overall_mshr_misses::cpu0.data 1250449 # number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_misses::total 1250449 # number of overall MSHR misses
+system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 21282308500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_latency::total 21282308500 # number of ReadReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 9459587261 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_latency::total 9459587261 # number of WriteReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::cpu0.data 170557000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency::total 170557000 # number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::cpu0.data 19849500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency::total 19849500 # number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 30741895761 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_latency::total 30741895761 # number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 30741895761 # number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_latency::total 30741895761 # number of overall MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::cpu0.data 1451668000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency::total 1451668000 # number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::cpu0.data 2155602499 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency::total 2155602499 # number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::cpu0.data 3607270499 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_mshr_uncacheable_latency::total 3607270499 # number of overall MSHR uncacheable cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.127024 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.127024 # mshr miss rate for ReadReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.050946 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.050946 # mshr miss rate for WriteReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::cpu0.data 0.088481 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate::total 0.088481 # mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::cpu0.data 0.020545 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate::total 0.020545 # mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_miss_rate::total 0.096419 # mshr miss rate for demand accesses
+system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.096419 # mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_miss_rate::total 0.096419 # mshr miss rate for overall accesses
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 21613.909093 # average ReadReq mshr miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 21613.909093 # average ReadReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 35590.321948 # average WriteReq mshr miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 35590.321948 # average WriteReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu0.data 11062.917559 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency::total 11062.917559 # average LoadLockedReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::cpu0.data 5321.581769 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency::total 5321.581769 # average StoreCondReq mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 24584.685790 # average overall mshr miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency::total 24584.685790 # average overall mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu0.data inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu0.data inf # average WriteReq mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::cpu0.data inf # average overall mshr uncacheable latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.branchPred.lookups 2951549 # Number of BP lookups
-system.cpu1.branchPred.condPredicted 2437718 # Number of conditional branches predicted
-system.cpu1.branchPred.condIncorrect 83271 # Number of conditional branches incorrect
-system.cpu1.branchPred.BTBLookups 1841355 # Number of BTB lookups
-system.cpu1.branchPred.BTBHits 993285 # Number of BTB hits
+system.cpu1.branchPred.lookups 2951275 # Number of BP lookups
+system.cpu1.branchPred.condPredicted 2437405 # Number of conditional branches predicted
+system.cpu1.branchPred.condIncorrect 83356 # Number of conditional branches incorrect
+system.cpu1.branchPred.BTBLookups 1836683 # Number of BTB lookups
+system.cpu1.branchPred.BTBHits 994148 # Number of BTB hits
system.cpu1.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu1.branchPred.BTBHitPct 53.943156 # BTB Hit Percentage
-system.cpu1.branchPred.usedRAS 204052 # Number of times the RAS was used to get a target.
-system.cpu1.branchPred.RASInCorrect 9178 # Number of incorrect RAS predictions.
+system.cpu1.branchPred.BTBHitPct 54.127359 # BTB Hit Percentage
+system.cpu1.branchPred.usedRAS 203977 # Number of times the RAS was used to get a target.
+system.cpu1.branchPred.RASInCorrect 9132 # Number of incorrect RAS predictions.
system.cpu1.dtb.fetch_hits 0 # ITB hits
system.cpu1.dtb.fetch_misses 0 # ITB misses
system.cpu1.dtb.fetch_acv 0 # ITB acv
system.cpu1.dtb.fetch_accesses 0 # ITB accesses
-system.cpu1.dtb.read_hits 2175312 # DTB read hits
-system.cpu1.dtb.read_misses 10933 # DTB read misses
-system.cpu1.dtb.read_acv 25 # DTB read access violations
-system.cpu1.dtb.read_accesses 324345 # DTB read accesses
-system.cpu1.dtb.write_hits 1433020 # DTB write hits
-system.cpu1.dtb.write_misses 2283 # DTB write misses
+system.cpu1.dtb.read_hits 2175721 # DTB read hits
+system.cpu1.dtb.read_misses 10990 # DTB read misses
+system.cpu1.dtb.read_acv 22 # DTB read access violations
+system.cpu1.dtb.read_accesses 324709 # DTB read accesses
+system.cpu1.dtb.write_hits 1432957 # DTB write hits
+system.cpu1.dtb.write_misses 2208 # DTB write misses
system.cpu1.dtb.write_acv 64 # DTB write access violations
-system.cpu1.dtb.write_accesses 133154 # DTB write accesses
-system.cpu1.dtb.data_hits 3608332 # DTB hits
-system.cpu1.dtb.data_misses 13216 # DTB misses
-system.cpu1.dtb.data_acv 89 # DTB access violations
-system.cpu1.dtb.data_accesses 457499 # DTB accesses
-system.cpu1.itb.fetch_hits 457840 # ITB hits
-system.cpu1.itb.fetch_misses 7553 # ITB misses
-system.cpu1.itb.fetch_acv 250 # ITB acv
-system.cpu1.itb.fetch_accesses 465393 # ITB accesses
+system.cpu1.dtb.write_accesses 133156 # DTB write accesses
+system.cpu1.dtb.data_hits 3608678 # DTB hits
+system.cpu1.dtb.data_misses 13198 # DTB misses
+system.cpu1.dtb.data_acv 86 # DTB access violations
+system.cpu1.dtb.data_accesses 457865 # DTB accesses
+system.cpu1.itb.fetch_hits 458401 # ITB hits
+system.cpu1.itb.fetch_misses 7664 # ITB misses
+system.cpu1.itb.fetch_acv 238 # ITB acv
+system.cpu1.itb.fetch_accesses 466065 # ITB accesses
system.cpu1.itb.read_hits 0 # DTB read hits
system.cpu1.itb.read_misses 0 # DTB read misses
system.cpu1.itb.read_acv 0 # DTB read access violations
system.cpu1.itb.data_misses 0 # DTB misses
system.cpu1.itb.data_acv 0 # DTB access violations
system.cpu1.itb.data_accesses 0 # DTB accesses
-system.cpu1.numCycles 18134862 # number of cpu cycles simulated
+system.cpu1.numCycles 18142763 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.fetch.icacheStallCycles 7058023 # Number of cycles fetch is stalled on an Icache miss
-system.cpu1.fetch.Insts 13901788 # Number of instructions fetch has processed
-system.cpu1.fetch.Branches 2951549 # Number of branches that fetch encountered
-system.cpu1.fetch.predictedBranches 1197337 # Number of branches that fetch has predicted taken
-system.cpu1.fetch.Cycles 2488361 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu1.fetch.SquashCycles 434606 # Number of cycles fetch has spent squashing
-system.cpu1.fetch.BlockedCycles 7030666 # Number of cycles fetch has spent blocked
-system.cpu1.fetch.MiscStallCycles 27606 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu1.fetch.PendingTrapStallCycles 66549 # Number of stall cycles due to pending traps
-system.cpu1.fetch.PendingQuiesceStallCycles 53385 # Number of stall cycles due to pending quiesce instructions
-system.cpu1.fetch.IcacheWaitRetryStallCycles 19 # Number of stall cycles due to full MSHR
-system.cpu1.fetch.CacheLines 1664870 # Number of cache lines fetched
-system.cpu1.fetch.IcacheSquashes 56635 # Number of outstanding Icache misses that were squashed
-system.cpu1.fetch.rateDist::samples 17000314 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::mean 0.817737 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::stdev 2.192147 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.icacheStallCycles 7059665 # Number of cycles fetch is stalled on an Icache miss
+system.cpu1.fetch.Insts 13904860 # Number of instructions fetch has processed
+system.cpu1.fetch.Branches 2951275 # Number of branches that fetch encountered
+system.cpu1.fetch.predictedBranches 1198125 # Number of branches that fetch has predicted taken
+system.cpu1.fetch.Cycles 2489767 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu1.fetch.SquashCycles 435348 # Number of cycles fetch has spent squashing
+system.cpu1.fetch.BlockedCycles 7028149 # Number of cycles fetch has spent blocked
+system.cpu1.fetch.MiscStallCycles 27735 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu1.fetch.PendingTrapStallCycles 66683 # Number of stall cycles due to pending traps
+system.cpu1.fetch.PendingQuiesceStallCycles 53717 # Number of stall cycles due to pending quiesce instructions
+system.cpu1.fetch.IcacheWaitRetryStallCycles 8 # Number of stall cycles due to full MSHR
+system.cpu1.fetch.CacheLines 1666090 # Number of cache lines fetched
+system.cpu1.fetch.IcacheSquashes 56854 # Number of outstanding Icache misses that were squashed
+system.cpu1.fetch.rateDist::samples 17001992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::mean 0.817837 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::stdev 2.192062 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::0 14511953 85.36% 85.36% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::1 164183 0.97% 86.33% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::2 263479 1.55% 87.88% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::3 196070 1.15% 89.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::4 340293 2.00% 91.03% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::5 131013 0.77% 91.80% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::6 146759 0.86% 92.67% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::7 246866 1.45% 94.12% # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::8 999698 5.88% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::0 14512225 85.36% 85.36% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::1 164132 0.97% 86.32% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::2 264549 1.56% 87.88% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::3 196224 1.15% 89.03% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::4 340931 2.01% 91.04% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::5 130664 0.77% 91.81% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::6 146583 0.86% 92.67% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::7 247056 1.45% 94.12% # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.rateDist::8 999628 5.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.rateDist::total 17000314 # Number of instructions fetched each cycle (Total)
-system.cpu1.fetch.branchRate 0.162756 # Number of branch fetches per cycle
-system.cpu1.fetch.rate 0.766578 # Number of inst fetches per cycle
-system.cpu1.decode.IdleCycles 6933279 # Number of cycles decode is idle
-system.cpu1.decode.BlockedCycles 7344422 # Number of cycles decode is blocked
-system.cpu1.decode.RunCycles 2325932 # Number of cycles decode is running
-system.cpu1.decode.UnblockCycles 129039 # Number of cycles decode is unblocking
-system.cpu1.decode.SquashCycles 267641 # Number of cycles decode is squashing
-system.cpu1.decode.BranchResolved 130064 # Number of times decode resolved a branch
-system.cpu1.decode.BranchMispred 8172 # Number of times decode detected a branch misprediction
-system.cpu1.decode.DecodedInsts 13645823 # Number of instructions handled by decode
-system.cpu1.decode.SquashedInsts 24424 # Number of squashed instructions handled by decode
-system.cpu1.rename.SquashCycles 267641 # Number of cycles rename is squashing
-system.cpu1.rename.IdleCycles 7167565 # Number of cycles rename is idle
-system.cpu1.rename.BlockCycles 532442 # Number of cycles rename is blocking
-system.cpu1.rename.serializeStallCycles 6090489 # count of cycles rename stalled for serializing inst
-system.cpu1.rename.RunCycles 2219281 # Number of cycles rename is running
-system.cpu1.rename.UnblockCycles 722894 # Number of cycles rename is unblocking
-system.cpu1.rename.RenamedInsts 12655848 # Number of instructions processed by rename
-system.cpu1.rename.ROBFullEvents 62 # Number of times rename has blocked due to ROB full
-system.cpu1.rename.IQFullEvents 62249 # Number of times rename has blocked due to IQ full
-system.cpu1.rename.LSQFullEvents 176645 # Number of times rename has blocked due to LSQ full
-system.cpu1.rename.RenamedOperands 8292237 # Number of destination operands rename has renamed
-system.cpu1.rename.RenameLookups 15046679 # Number of register rename lookups that rename has made
-system.cpu1.rename.int_rename_lookups 14871812 # Number of integer rename lookups
-system.cpu1.rename.fp_rename_lookups 174867 # Number of floating rename lookups
-system.cpu1.rename.CommittedMaps 7154777 # Number of HB maps that are committed
-system.cpu1.rename.UndoneMaps 1137460 # Number of HB maps that are undone due to squashing
-system.cpu1.rename.serializingInsts 507049 # count of serializing insts renamed
-system.cpu1.rename.tempSerializingInsts 51410 # count of temporary serializing insts renamed
-system.cpu1.rename.skidInsts 2247669 # count of insts added to the skid buffer
-system.cpu1.memDep0.insertedLoads 2296294 # Number of loads inserted to the mem dependence unit.
-system.cpu1.memDep0.insertedStores 1513309 # Number of stores inserted to the mem dependence unit.
-system.cpu1.memDep0.conflictingLoads 213499 # Number of conflicting loads.
-system.cpu1.memDep0.conflictingStores 120116 # Number of conflicting stores.
-system.cpu1.iq.iqInstsAdded 11096018 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu1.iq.iqNonSpecInstsAdded 565266 # Number of non-speculative instructions added to the IQ
-system.cpu1.iq.iqInstsIssued 10828805 # Number of instructions issued
-system.cpu1.iq.iqSquashedInstsIssued 31328 # Number of squashed instructions issued
-system.cpu1.iq.iqSquashedInstsExamined 1532737 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu1.iq.iqSquashedOperandsExamined 753738 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu1.iq.iqSquashedNonSpecRemoved 401627 # Number of squashed non-spec instructions that were removed
-system.cpu1.iq.issued_per_cycle::samples 17000314 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::mean 0.636977 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::stdev 1.310793 # Number of insts issued each cycle
+system.cpu1.fetch.rateDist::total 17001992 # Number of instructions fetched each cycle (Total)
+system.cpu1.fetch.branchRate 0.162670 # Number of branch fetches per cycle
+system.cpu1.fetch.rate 0.766414 # Number of inst fetches per cycle
+system.cpu1.decode.IdleCycles 6935204 # Number of cycles decode is idle
+system.cpu1.decode.BlockedCycles 7342187 # Number of cycles decode is blocked
+system.cpu1.decode.RunCycles 2328189 # Number of cycles decode is running
+system.cpu1.decode.UnblockCycles 128213 # Number of cycles decode is unblocking
+system.cpu1.decode.SquashCycles 268198 # Number of cycles decode is squashing
+system.cpu1.decode.BranchResolved 130237 # Number of times decode resolved a branch
+system.cpu1.decode.BranchMispred 8176 # Number of times decode detected a branch misprediction
+system.cpu1.decode.DecodedInsts 13648246 # Number of instructions handled by decode
+system.cpu1.decode.SquashedInsts 24564 # Number of squashed instructions handled by decode
+system.cpu1.rename.SquashCycles 268198 # Number of cycles rename is squashing
+system.cpu1.rename.IdleCycles 7169583 # Number of cycles rename is idle
+system.cpu1.rename.BlockCycles 530321 # Number of cycles rename is blocking
+system.cpu1.rename.serializeStallCycles 6090332 # count of cycles rename stalled for serializing inst
+system.cpu1.rename.RunCycles 2220482 # Number of cycles rename is running
+system.cpu1.rename.UnblockCycles 723074 # Number of cycles rename is unblocking
+system.cpu1.rename.RenamedInsts 12659443 # Number of instructions processed by rename
+system.cpu1.rename.ROBFullEvents 49 # Number of times rename has blocked due to ROB full
+system.cpu1.rename.IQFullEvents 62425 # Number of times rename has blocked due to IQ full
+system.cpu1.rename.LSQFullEvents 176745 # Number of times rename has blocked due to LSQ full
+system.cpu1.rename.RenamedOperands 8295078 # Number of destination operands rename has renamed
+system.cpu1.rename.RenameLookups 15050859 # Number of register rename lookups that rename has made
+system.cpu1.rename.int_rename_lookups 14876046 # Number of integer rename lookups
+system.cpu1.rename.fp_rename_lookups 174813 # Number of floating rename lookups
+system.cpu1.rename.CommittedMaps 7154813 # Number of HB maps that are committed
+system.cpu1.rename.UndoneMaps 1140265 # Number of HB maps that are undone due to squashing
+system.cpu1.rename.serializingInsts 506846 # count of serializing insts renamed
+system.cpu1.rename.tempSerializingInsts 51390 # count of temporary serializing insts renamed
+system.cpu1.rename.skidInsts 2247067 # count of insts added to the skid buffer
+system.cpu1.memDep0.insertedLoads 2298271 # Number of loads inserted to the mem dependence unit.
+system.cpu1.memDep0.insertedStores 1513317 # Number of stores inserted to the mem dependence unit.
+system.cpu1.memDep0.conflictingLoads 213048 # Number of conflicting loads.
+system.cpu1.memDep0.conflictingStores 119189 # Number of conflicting stores.
+system.cpu1.iq.iqInstsAdded 11099753 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu1.iq.iqNonSpecInstsAdded 565057 # Number of non-speculative instructions added to the IQ
+system.cpu1.iq.iqInstsIssued 10829119 # Number of instructions issued
+system.cpu1.iq.iqSquashedInstsIssued 31632 # Number of squashed instructions issued
+system.cpu1.iq.iqSquashedInstsExamined 1536258 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu1.iq.iqSquashedOperandsExamined 758334 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu1.iq.iqSquashedNonSpecRemoved 401417 # Number of squashed non-spec instructions that were removed
+system.cpu1.iq.issued_per_cycle::samples 17001992 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::mean 0.636932 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::stdev 1.310611 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::0 12224627 71.91% 71.91% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::1 2204627 12.97% 84.88% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::2 929274 5.47% 90.34% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::3 621491 3.66% 94.00% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::4 537457 3.16% 97.16% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::5 242471 1.43% 98.59% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::6 153482 0.90% 99.49% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::7 76998 0.45% 99.94% # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::8 9887 0.06% 100.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::0 12225446 71.91% 71.91% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::1 2205450 12.97% 84.88% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::2 929224 5.47% 90.34% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::3 621702 3.66% 94.00% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::4 537509 3.16% 97.16% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::5 242497 1.43% 98.59% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::6 153407 0.90% 99.49% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::7 76904 0.45% 99.94% # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::8 9853 0.06% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu1.iq.issued_per_cycle::total 17000314 # Number of insts issued each cycle
+system.cpu1.iq.issued_per_cycle::total 17001992 # Number of insts issued each cycle
system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntAlu 3882 1.79% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntMult 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.79% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemRead 115382 53.28% 55.07% # attempts to use FU when none available
-system.cpu1.iq.fu_full::MemWrite 97306 44.93% 100.00% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntAlu 3913 1.80% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntMult 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::IntDiv 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatAdd 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCmp 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatCvt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatMult 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatDiv 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAdd 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdAlu 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCmp 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdCvt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMisc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMult 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShift 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 1.80% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemRead 115549 53.23% 55.03% # attempts to use FU when none available
+system.cpu1.iq.fu_full::MemWrite 97618 44.97% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
system.cpu1.iq.FU_type_0::No_OpClass 3526 0.03% 0.03% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntAlu 6757278 62.40% 62.43% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntMult 17931 0.17% 62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.60% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.71% # Type of FU issued
-system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.71% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntAlu 6756968 62.40% 62.43% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntMult 17928 0.17% 62.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 62.59% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatAdd 11481 0.11% 62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 62.70% # Type of FU issued
+system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 62.70% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatDiv 1763 0.02% 62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 62.72% # Type of FU issued
system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 62.72% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemRead 2277505 21.03% 83.75% # Type of FU issued
-system.cpu1.iq.FU_type_0::MemWrite 1457876 13.46% 97.22% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemRead 2278200 21.04% 83.75% # Type of FU issued
+system.cpu1.iq.FU_type_0::MemWrite 1457808 13.46% 97.22% # Type of FU issued
system.cpu1.iq.FU_type_0::IprAccess 301445 2.78% 100.00% # Type of FU issued
system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu1.iq.FU_type_0::total 10828805 # Type of FU issued
-system.cpu1.iq.rate 0.597126 # Inst issue rate
-system.cpu1.iq.fu_busy_cnt 216570 # FU busy when requested
-system.cpu1.iq.fu_busy_rate 0.019999 # FU busy rate (busy events/executed inst)
-system.cpu1.iq.int_inst_queue_reads 38654254 # Number of integer instruction queue reads
-system.cpu1.iq.int_inst_queue_writes 13073033 # Number of integer instruction queue writes
-system.cpu1.iq.int_inst_queue_wakeup_accesses 10523817 # Number of integer instruction queue wakeup accesses
-system.cpu1.iq.fp_inst_queue_reads 251568 # Number of floating instruction queue reads
-system.cpu1.iq.fp_inst_queue_writes 122847 # Number of floating instruction queue writes
-system.cpu1.iq.fp_inst_queue_wakeup_accesses 119196 # Number of floating instruction queue wakeup accesses
-system.cpu1.iq.int_alu_accesses 10910865 # Number of integer alu accesses
-system.cpu1.iq.fp_alu_accesses 130984 # Number of floating point alu accesses
-system.cpu1.iew.lsq.thread0.forwLoads 103558 # Number of loads that had data forwarded from stores
+system.cpu1.iq.FU_type_0::total 10829119 # Type of FU issued
+system.cpu1.iq.rate 0.596884 # Inst issue rate
+system.cpu1.iq.fu_busy_cnt 217080 # FU busy when requested
+system.cpu1.iq.fu_busy_rate 0.020046 # FU busy rate (busy events/executed inst)
+system.cpu1.iq.int_inst_queue_reads 38657394 # Number of integer instruction queue reads
+system.cpu1.iq.int_inst_queue_writes 13080099 # Number of integer instruction queue writes
+system.cpu1.iq.int_inst_queue_wakeup_accesses 10523969 # Number of integer instruction queue wakeup accesses
+system.cpu1.iq.fp_inst_queue_reads 251548 # Number of floating instruction queue reads
+system.cpu1.iq.fp_inst_queue_writes 122819 # Number of floating instruction queue writes
+system.cpu1.iq.fp_inst_queue_wakeup_accesses 119141 # Number of floating instruction queue wakeup accesses
+system.cpu1.iq.int_alu_accesses 10911695 # Number of integer alu accesses
+system.cpu1.iq.fp_alu_accesses 130978 # Number of floating point alu accesses
+system.cpu1.iew.lsq.thread0.forwLoads 103489 # Number of loads that had data forwarded from stores
system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu1.iew.lsq.thread0.squashedLoads 299992 # Number of loads squashed
-system.cpu1.iew.lsq.thread0.ignoredResponses 506 # Number of memory responses ignored because the instruction is squashed
-system.cpu1.iew.lsq.thread0.memOrderViolation 1941 # Number of memory ordering violations
-system.cpu1.iew.lsq.thread0.squashedStores 130288 # Number of stores squashed
+system.cpu1.iew.lsq.thread0.squashedLoads 301882 # Number of loads squashed
+system.cpu1.iew.lsq.thread0.ignoredResponses 508 # Number of memory responses ignored because the instruction is squashed
+system.cpu1.iew.lsq.thread0.memOrderViolation 1924 # Number of memory ordering violations
+system.cpu1.iew.lsq.thread0.squashedStores 130297 # Number of stores squashed
system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu1.iew.lsq.thread0.rescheduledLoads 384 # Number of loads that were rescheduled
-system.cpu1.iew.lsq.thread0.cacheBlocked 9585 # Number of times an access to memory failed due to the cache being blocked
+system.cpu1.iew.lsq.thread0.rescheduledLoads 383 # Number of loads that were rescheduled
+system.cpu1.iew.lsq.thread0.cacheBlocked 9692 # Number of times an access to memory failed due to the cache being blocked
system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu1.iew.iewSquashCycles 267641 # Number of cycles IEW is squashing
-system.cpu1.iew.iewBlockCycles 350754 # Number of cycles IEW is blocking
-system.cpu1.iew.iewUnblockCycles 52140 # Number of cycles IEW is unblocking
-system.cpu1.iew.iewDispatchedInsts 12262013 # Number of instructions dispatched to IQ
-system.cpu1.iew.iewDispSquashedInsts 164906 # Number of squashed instructions skipped by dispatch
-system.cpu1.iew.iewDispLoadInsts 2296294 # Number of dispatched load instructions
-system.cpu1.iew.iewDispStoreInsts 1513309 # Number of dispatched store instructions
-system.cpu1.iew.iewDispNonSpecInsts 509197 # Number of dispatched non-speculative instructions
-system.cpu1.iew.iewIQFullEvents 44334 # Number of times the IQ has become full, causing a stall
-system.cpu1.iew.iewLSQFullEvents 2198 # Number of times the LSQ has become full, causing a stall
-system.cpu1.iew.memOrderViolationEvents 1941 # Number of memory order violations
-system.cpu1.iew.predictedTakenIncorrect 37737 # Number of branches that were predicted taken incorrectly
-system.cpu1.iew.predictedNotTakenIncorrect 111746 # Number of branches that were predicted not taken incorrectly
-system.cpu1.iew.branchMispredicts 149483 # Number of branch mispredicts detected at execute
-system.cpu1.iew.iewExecutedInsts 10726014 # Number of executed instructions
-system.cpu1.iew.iewExecLoadInsts 2194881 # Number of load instructions executed
-system.cpu1.iew.iewExecSquashedInsts 102791 # Number of squashed instructions skipped in execute
+system.cpu1.iew.iewSquashCycles 268198 # Number of cycles IEW is squashing
+system.cpu1.iew.iewBlockCycles 347966 # Number of cycles IEW is blocking
+system.cpu1.iew.iewUnblockCycles 52179 # Number of cycles IEW is unblocking
+system.cpu1.iew.iewDispatchedInsts 12265641 # Number of instructions dispatched to IQ
+system.cpu1.iew.iewDispSquashedInsts 165598 # Number of squashed instructions skipped by dispatch
+system.cpu1.iew.iewDispLoadInsts 2298271 # Number of dispatched load instructions
+system.cpu1.iew.iewDispStoreInsts 1513317 # Number of dispatched store instructions
+system.cpu1.iew.iewDispNonSpecInsts 508976 # Number of dispatched non-speculative instructions
+system.cpu1.iew.iewIQFullEvents 44383 # Number of times the IQ has become full, causing a stall
+system.cpu1.iew.iewLSQFullEvents 2331 # Number of times the LSQ has become full, causing a stall
+system.cpu1.iew.memOrderViolationEvents 1924 # Number of memory order violations
+system.cpu1.iew.predictedTakenIncorrect 37819 # Number of branches that were predicted taken incorrectly
+system.cpu1.iew.predictedNotTakenIncorrect 111790 # Number of branches that were predicted not taken incorrectly
+system.cpu1.iew.branchMispredicts 149609 # Number of branch mispredicts detected at execute
+system.cpu1.iew.iewExecutedInsts 10726333 # Number of executed instructions
+system.cpu1.iew.iewExecLoadInsts 2195343 # Number of load instructions executed
+system.cpu1.iew.iewExecSquashedInsts 102786 # Number of squashed instructions skipped in execute
system.cpu1.iew.exec_swp 0 # number of swp insts executed
-system.cpu1.iew.exec_nop 600729 # number of nop insts executed
-system.cpu1.iew.exec_refs 3637088 # number of memory reference insts executed
-system.cpu1.iew.exec_branches 1609931 # Number of branches executed
-system.cpu1.iew.exec_stores 1442207 # Number of stores executed
-system.cpu1.iew.exec_rate 0.591458 # Inst execution rate
-system.cpu1.iew.wb_sent 10671299 # cumulative count of insts sent to commit
-system.cpu1.iew.wb_count 10643013 # cumulative count of insts written-back
-system.cpu1.iew.wb_producers 4954529 # num instructions producing a value
-system.cpu1.iew.wb_consumers 6965334 # num instructions consuming a value
+system.cpu1.iew.exec_nop 600831 # number of nop insts executed
+system.cpu1.iew.exec_refs 3637407 # number of memory reference insts executed
+system.cpu1.iew.exec_branches 1609945 # Number of branches executed
+system.cpu1.iew.exec_stores 1442064 # Number of stores executed
+system.cpu1.iew.exec_rate 0.591218 # Inst execution rate
+system.cpu1.iew.wb_sent 10671459 # cumulative count of insts sent to commit
+system.cpu1.iew.wb_count 10643110 # cumulative count of insts written-back
+system.cpu1.iew.wb_producers 4954176 # num instructions producing a value
+system.cpu1.iew.wb_consumers 6965889 # num instructions consuming a value
system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu1.iew.wb_rate 0.586881 # insts written-back per cycle
-system.cpu1.iew.wb_fanout 0.711312 # average fanout of values written-back
+system.cpu1.iew.wb_rate 0.586631 # insts written-back per cycle
+system.cpu1.iew.wb_fanout 0.711205 # average fanout of values written-back
system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu1.commit.commitSquashedInsts 1577214 # The number of squashed insts skipped by commit
-system.cpu1.commit.commitNonSpecStalls 163639 # The number of times commit has been forced to stall to communicate backwards
-system.cpu1.commit.branchMispredicts 139875 # The number of times a branch was mispredicted
-system.cpu1.commit.committed_per_cycle::samples 16732673 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::mean 0.633048 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::stdev 1.579888 # Number of insts commited each cycle
+system.cpu1.commit.commitSquashedInsts 1581528 # The number of squashed insts skipped by commit
+system.cpu1.commit.commitNonSpecStalls 163640 # The number of times commit has been forced to stall to communicate backwards
+system.cpu1.commit.branchMispredicts 139954 # The number of times a branch was mispredicted
+system.cpu1.commit.committed_per_cycle::samples 16733794 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::mean 0.633013 # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::stdev 1.579692 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::0 12788613 76.43% 76.43% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::1 1829501 10.93% 87.36% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::2 688548 4.11% 91.48% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::3 419965 2.51% 93.99% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::4 300741 1.80% 95.78% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::5 117837 0.70% 96.49% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::6 119533 0.71% 97.20% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::7 126738 0.76% 97.96% # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::8 341197 2.04% 100.00% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::0 12789139 76.43% 76.43% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::1 1829893 10.94% 87.36% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::2 688745 4.12% 91.48% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::3 420012 2.51% 93.99% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::4 300647 1.80% 95.78% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::5 117990 0.71% 96.49% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::6 119790 0.72% 97.21% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::7 126616 0.76% 97.96% # Number of insts commited each cycle
+system.cpu1.commit.committed_per_cycle::8 340962 2.04% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu1.commit.committed_per_cycle::total 16732673 # Number of insts commited each cycle
-system.cpu1.commit.committedInsts 10592581 # Number of instructions committed
-system.cpu1.commit.committedOps 10592581 # Number of ops (including micro ops) committed
+system.cpu1.commit.committed_per_cycle::total 16733794 # Number of insts commited each cycle
+system.cpu1.commit.committedInsts 10592705 # Number of instructions committed
+system.cpu1.commit.committedOps 10592705 # Number of ops (including micro ops) committed
system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu1.commit.refs 3379323 # Number of memory references committed
-system.cpu1.commit.loads 1996302 # Number of loads committed
+system.cpu1.commit.refs 3379409 # Number of memory references committed
+system.cpu1.commit.loads 1996389 # Number of loads committed
system.cpu1.commit.membars 53397 # Number of memory barriers committed
-system.cpu1.commit.branches 1516852 # Number of branches committed
+system.cpu1.commit.branches 1516939 # Number of branches committed
system.cpu1.commit.fp_insts 117937 # Number of committed floating point instructions.
-system.cpu1.commit.int_insts 9798554 # Number of committed integer instructions.
+system.cpu1.commit.int_insts 9798676 # Number of committed integer instructions.
system.cpu1.commit.function_calls 169964 # Number of function calls committed.
-system.cpu1.commit.bw_lim_events 341197 # number cycles where commit BW limit reached
+system.cpu1.commit.bw_lim_events 340962 # number cycles where commit BW limit reached
system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu1.rob.rob_reads 28468767 # The number of ROB reads
-system.cpu1.rob.rob_writes 24605693 # The number of ROB writes
-system.cpu1.timesIdled 153691 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu1.idleCycles 1134548 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu1.quiesceCycles 3782736336 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu1.committedInsts 10061892 # Number of Instructions Simulated
-system.cpu1.committedOps 10061892 # Number of Ops (including micro ops) Simulated
-system.cpu1.committedInsts_total 10061892 # Number of Instructions Simulated
-system.cpu1.cpi 1.802331 # CPI: Cycles Per Instruction
-system.cpu1.cpi_total 1.802331 # CPI: Total CPI of All Threads
-system.cpu1.ipc 0.554837 # IPC: Instructions Per Cycle
-system.cpu1.ipc_total 0.554837 # IPC: Total IPC of All Threads
-system.cpu1.int_regfile_reads 13798288 # number of integer regfile reads
-system.cpu1.int_regfile_writes 7546279 # number of integer regfile writes
-system.cpu1.fp_regfile_reads 63929 # number of floating regfile reads
-system.cpu1.fp_regfile_writes 63981 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 608468 # number of misc regfile reads
+system.cpu1.rob.rob_reads 28474562 # The number of ROB reads
+system.cpu1.rob.rob_writes 24615096 # The number of ROB writes
+system.cpu1.timesIdled 153586 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu1.idleCycles 1140771 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu1.quiesceCycles 3782727730 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu1.committedInsts 10062016 # Number of Instructions Simulated
+system.cpu1.committedOps 10062016 # Number of Ops (including micro ops) Simulated
+system.cpu1.committedInsts_total 10062016 # Number of Instructions Simulated
+system.cpu1.cpi 1.803094 # CPI: Cycles Per Instruction
+system.cpu1.cpi_total 1.803094 # CPI: Total CPI of All Threads
+system.cpu1.ipc 0.554602 # IPC: Instructions Per Cycle
+system.cpu1.ipc_total 0.554602 # IPC: Total IPC of All Threads
+system.cpu1.int_regfile_reads 13798564 # number of integer regfile reads
+system.cpu1.int_regfile_writes 7546386 # number of integer regfile writes
+system.cpu1.fp_regfile_reads 63884 # number of floating regfile reads
+system.cpu1.fp_regfile_writes 63971 # number of floating regfile writes
+system.cpu1.misc_regfile_reads 608483 # number of misc regfile reads
system.cpu1.misc_regfile_writes 251084 # number of misc regfile writes
-system.cpu1.icache.replacements 263438 # number of replacements
-system.cpu1.icache.tagsinuse 470.047000 # Cycle average of tags in use
-system.cpu1.icache.total_refs 1391700 # Total number of references to valid blocks.
-system.cpu1.icache.sampled_refs 263950 # Sample count of references to valid blocks.
-system.cpu1.icache.avg_refs 5.272590 # Average number of references to valid blocks.
-system.cpu1.icache.warmup_cycle 1875178456000 # Cycle when the warmup percentage was hit.
-system.cpu1.icache.occ_blocks::cpu1.inst 470.047000 # Average occupied blocks per requestor
+system.cpu1.icache.replacements 263412 # number of replacements
+system.cpu1.icache.tagsinuse 470.047023 # Cycle average of tags in use
+system.cpu1.icache.total_refs 1392951 # Total number of references to valid blocks.
+system.cpu1.icache.sampled_refs 263924 # Sample count of references to valid blocks.
+system.cpu1.icache.avg_refs 5.277849 # Average number of references to valid blocks.
+system.cpu1.icache.warmup_cycle 1875177958000 # Cycle when the warmup percentage was hit.
+system.cpu1.icache.occ_blocks::cpu1.inst 470.047023 # Average occupied blocks per requestor
system.cpu1.icache.occ_percent::cpu1.inst 0.918061 # Average percentage of cache occupancy
system.cpu1.icache.occ_percent::total 0.918061 # Average percentage of cache occupancy
-system.cpu1.icache.ReadReq_hits::cpu1.inst 1391700 # number of ReadReq hits
-system.cpu1.icache.ReadReq_hits::total 1391700 # number of ReadReq hits
-system.cpu1.icache.demand_hits::cpu1.inst 1391700 # number of demand (read+write) hits
-system.cpu1.icache.demand_hits::total 1391700 # number of demand (read+write) hits
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-system.cpu1.icache.overall_hits::total 1391700 # number of overall hits
-system.cpu1.icache.ReadReq_misses::cpu1.inst 273170 # number of ReadReq misses
-system.cpu1.icache.ReadReq_misses::total 273170 # number of ReadReq misses
-system.cpu1.icache.demand_misses::cpu1.inst 273170 # number of demand (read+write) misses
-system.cpu1.icache.demand_misses::total 273170 # number of demand (read+write) misses
-system.cpu1.icache.overall_misses::cpu1.inst 273170 # number of overall misses
-system.cpu1.icache.overall_misses::total 273170 # number of overall misses
-system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 3762343999 # number of ReadReq miss cycles
-system.cpu1.icache.ReadReq_miss_latency::total 3762343999 # number of ReadReq miss cycles
-system.cpu1.icache.demand_miss_latency::cpu1.inst 3762343999 # number of demand (read+write) miss cycles
-system.cpu1.icache.demand_miss_latency::total 3762343999 # number of demand (read+write) miss cycles
-system.cpu1.icache.overall_miss_latency::cpu1.inst 3762343999 # number of overall miss cycles
-system.cpu1.icache.overall_miss_latency::total 3762343999 # number of overall miss cycles
-system.cpu1.icache.ReadReq_accesses::cpu1.inst 1664870 # number of ReadReq accesses(hits+misses)
-system.cpu1.icache.ReadReq_accesses::total 1664870 # number of ReadReq accesses(hits+misses)
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-system.cpu1.icache.demand_accesses::total 1664870 # number of demand (read+write) accesses
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-system.cpu1.icache.overall_accesses::total 1664870 # number of overall (read+write) accesses
-system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.164079 # miss rate for ReadReq accesses
-system.cpu1.icache.ReadReq_miss_rate::total 0.164079 # miss rate for ReadReq accesses
-system.cpu1.icache.demand_miss_rate::cpu1.inst 0.164079 # miss rate for demand accesses
-system.cpu1.icache.demand_miss_rate::total 0.164079 # miss rate for demand accesses
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-system.cpu1.icache.overall_miss_rate::total 0.164079 # miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 13772.903317 # average ReadReq miss latency
-system.cpu1.icache.ReadReq_avg_miss_latency::total 13772.903317 # average ReadReq miss latency
-system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency
-system.cpu1.icache.demand_avg_miss_latency::total 13772.903317 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13772.903317 # average overall miss latency
-system.cpu1.icache.overall_avg_miss_latency::total 13772.903317 # average overall miss latency
-system.cpu1.icache.blocked_cycles::no_mshrs 900 # number of cycles access was blocked
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+system.cpu1.icache.overall_misses::total 273139 # number of overall misses
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+system.cpu1.icache.ReadReq_miss_latency::total 3753112000 # number of ReadReq miss cycles
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+system.cpu1.icache.ReadReq_avg_miss_latency::total 13740.666840 # average ReadReq miss latency
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+system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 13740.666840 # average overall miss latency
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system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu1.icache.blocked::no_mshrs 21 # number of cycles access was blocked
+system.cpu1.icache.blocked::no_mshrs 18 # number of cycles access was blocked
system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.icache.fast_writes 0 # number of fast writes performed
system.cpu1.icache.cache_copies 0 # number of cache copies performed
-system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 9145 # number of ReadReq MSHR hits
-system.cpu1.icache.ReadReq_mshr_hits::total 9145 # number of ReadReq MSHR hits
-system.cpu1.icache.demand_mshr_hits::cpu1.inst 9145 # number of demand (read+write) MSHR hits
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-system.cpu1.icache.overall_mshr_hits::total 9145 # number of overall MSHR hits
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-system.cpu1.icache.ReadReq_mshr_miss_latency::total 3130972999 # number of ReadReq MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3130972999 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.demand_mshr_miss_latency::total 3130972999 # number of demand (read+write) MSHR miss cycles
-system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 3130972999 # number of overall MSHR miss cycles
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-system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.158586 # mshr miss rate for ReadReq accesses
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-system.cpu1.icache.demand_mshr_miss_rate::total 0.158586 # mshr miss rate for demand accesses
-system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158586 # mshr miss rate for overall accesses
-system.cpu1.icache.overall_mshr_miss_rate::total 0.158586 # mshr miss rate for overall accesses
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average ReadReq mshr miss latency
-system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11858.623233 # average ReadReq mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency
-system.cpu1.icache.demand_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11858.623233 # average overall mshr miss latency
-system.cpu1.icache.overall_avg_mshr_miss_latency::total 11858.623233 # average overall mshr miss latency
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+system.cpu1.icache.ReadReq_mshr_miss_latency::total 3126547000 # number of ReadReq MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 3126547000 # number of demand (read+write) MSHR miss cycles
+system.cpu1.icache.demand_mshr_miss_latency::total 3126547000 # number of demand (read+write) MSHR miss cycles
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+system.cpu1.icache.overall_mshr_miss_latency::total 3126547000 # number of overall MSHR miss cycles
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+system.cpu1.icache.demand_mshr_miss_rate::total 0.158452 # mshr miss rate for demand accesses
+system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.158452 # mshr miss rate for overall accesses
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+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average ReadReq mshr miss latency
+system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 11843.205364 # average ReadReq mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
+system.cpu1.icache.demand_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 11843.205364 # average overall mshr miss latency
+system.cpu1.icache.overall_avg_mshr_miss_latency::total 11843.205364 # average overall mshr miss latency
system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate
-system.cpu1.dcache.replacements 126485 # number of replacements
-system.cpu1.dcache.tagsinuse 490.826755 # Cycle average of tags in use
-system.cpu1.dcache.total_refs 2951833 # Total number of references to valid blocks.
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-system.cpu1.dcache.avg_refs 23.262929 # Average number of references to valid blocks.
+system.cpu1.dcache.replacements 126526 # number of replacements
+system.cpu1.dcache.tagsinuse 490.827782 # Cycle average of tags in use
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+system.cpu1.dcache.avg_refs 23.257132 # Average number of references to valid blocks.
system.cpu1.dcache.warmup_cycle 37142562000 # Cycle when the warmup percentage was hit.
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-system.cpu1.dcache.LoadLockedReq_hits::total 39938 # number of LoadLockedReq hits
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-system.cpu1.dcache.StoreCondReq_hits::total 38621 # number of StoreCondReq hits
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+system.cpu1.dcache.demand_miss_latency::total 11888847631 # number of demand (read+write) miss cycles
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system.cpu1.dcache.WriteReq_accesses::cpu1.data 1334016 # number of WriteReq accesses(hits+misses)
system.cpu1.dcache.WriteReq_accesses::total 1334016 # number of WriteReq accesses(hits+misses)
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-system.cpu1.dcache.LoadLockedReq_accesses::total 46567 # number of LoadLockedReq accesses(hits+misses)
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-system.cpu1.dcache.ReadReq_miss_rate::total 0.119851 # miss rate for ReadReq accesses
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-system.cpu1.dcache.WriteReq_miss_rate::total 0.188501 # miss rate for WriteReq accesses
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-system.cpu1.dcache.LoadLockedReq_miss_rate::total 0.142354 # miss rate for LoadLockedReq accesses
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-system.cpu1.dcache.overall_miss_rate::total 0.147104 # miss rate for overall accesses
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-system.cpu1.dcache.WriteReq_avg_miss_latency::total 32256.887041 # average WriteReq miss latency
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-system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10211.494946 # average LoadLockedReq miss latency
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-system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7342.138524 # average StoreCondReq miss latency
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-system.cpu1.dcache.demand_avg_miss_latency::total 23847.148698 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 23847.148698 # average overall miss latency
-system.cpu1.dcache.overall_avg_miss_latency::total 23847.148698 # average overall miss latency
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+system.cpu1.dcache.ReadReq_miss_rate::total 0.119893 # miss rate for ReadReq accesses
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+system.cpu1.dcache.WriteReq_miss_rate::total 0.188471 # miss rate for WriteReq accesses
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+system.cpu1.dcache.ReadReq_avg_miss_latency::total 15085.795419 # average ReadReq miss latency
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+system.cpu1.dcache.WriteReq_avg_miss_latency::total 32706.735784 # average WriteReq miss latency
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+system.cpu1.dcache.LoadLockedReq_avg_miss_latency::total 10213.628132 # average LoadLockedReq miss latency
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+system.cpu1.dcache.StoreCondReq_avg_miss_latency::total 7338.766742 # average StoreCondReq miss latency
+system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
+system.cpu1.dcache.demand_avg_miss_latency::total 24046.632803 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 24046.632803 # average overall miss latency
+system.cpu1.dcache.overall_avg_miss_latency::total 24046.632803 # average overall miss latency
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system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu1.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu1.dcache.fast_writes 0 # number of fast writes performed
system.cpu1.dcache.cache_copies 0 # number of cache copies performed
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-system.cpu1.dcache.writebacks::total 84853 # number of writebacks
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-system.cpu1.dcache.ReadReq_mshr_hits::total 150731 # number of ReadReq MSHR hits
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-system.cpu1.dcache.overall_mshr_hits::total 356363 # number of overall MSHR hits
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-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26421.646637 # average WriteReq mshr miss latency
-system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26421.646637 # average WriteReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7952.138323 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7952.138323 # average LoadLockedReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5342.138524 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5342.138524 # average StoreCondReq mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
-system.cpu1.dcache.demand_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 16918.599500 # average overall mshr miss latency
-system.cpu1.dcache.overall_avg_mshr_miss_latency::total 16918.599500 # average overall mshr miss latency
+system.cpu1.dcache.writebacks::writebacks 84886 # number of writebacks
+system.cpu1.dcache.writebacks::total 84886 # number of writebacks
+system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 150812 # number of ReadReq MSHR hits
+system.cpu1.dcache.ReadReq_mshr_hits::total 150812 # number of ReadReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 205594 # number of WriteReq MSHR hits
+system.cpu1.dcache.WriteReq_mshr_hits::total 205594 # number of WriteReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::cpu1.data 644 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.LoadLockedReq_mshr_hits::total 644 # number of LoadLockedReq MSHR hits
+system.cpu1.dcache.demand_mshr_hits::cpu1.data 356406 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.demand_mshr_hits::total 356406 # number of demand (read+write) MSHR hits
+system.cpu1.dcache.overall_mshr_hits::cpu1.data 356406 # number of overall MSHR hits
+system.cpu1.dcache.overall_mshr_hits::total 356406 # number of overall MSHR hits
+system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 92173 # number of ReadReq MSHR misses
+system.cpu1.dcache.ReadReq_mshr_misses::total 92173 # number of ReadReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 45829 # number of WriteReq MSHR misses
+system.cpu1.dcache.WriteReq_mshr_misses::total 45829 # number of WriteReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::cpu1.data 5982 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.LoadLockedReq_mshr_misses::total 5982 # number of LoadLockedReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::cpu1.data 3957 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.StoreCondReq_mshr_misses::total 3957 # number of StoreCondReq MSHR misses
+system.cpu1.dcache.demand_mshr_misses::cpu1.data 138002 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.demand_mshr_misses::total 138002 # number of demand (read+write) MSHR misses
+system.cpu1.dcache.overall_mshr_misses::cpu1.data 138002 # number of overall MSHR misses
+system.cpu1.dcache.overall_mshr_misses::total 138002 # number of overall MSHR misses
+system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1122474000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1122474000 # number of ReadReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1228877987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1228877987 # number of WriteReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::cpu1.data 47579000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.LoadLockedReq_mshr_miss_latency::total 47579000 # number of LoadLockedReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::cpu1.data 21125500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.StoreCondReq_mshr_miss_latency::total 21125500 # number of StoreCondReq MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2351351987 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.demand_mshr_miss_latency::total 2351351987 # number of demand (read+write) MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2351351987 # number of overall MSHR miss cycles
+system.cpu1.dcache.overall_mshr_miss_latency::total 2351351987 # number of overall MSHR miss cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::cpu1.data 30976000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_uncacheable_latency::total 30976000 # number of ReadReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::cpu1.data 675219000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.WriteReq_mshr_uncacheable_latency::total 675219000 # number of WriteReq MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::cpu1.data 706195000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.overall_mshr_uncacheable_latency::total 706195000 # number of overall MSHR uncacheable cycles
+system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.045480 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.045480 # mshr miss rate for ReadReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.034354 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.034354 # mshr miss rate for WriteReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::cpu1.data 0.128474 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.LoadLockedReq_mshr_miss_rate::total 0.128474 # mshr miss rate for LoadLockedReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::cpu1.data 0.092940 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.StoreCondReq_mshr_miss_rate::total 0.092940 # mshr miss rate for StoreCondReq accesses
+system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for demand accesses
+system.cpu1.dcache.demand_mshr_miss_rate::total 0.041063 # mshr miss rate for demand accesses
+system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.041063 # mshr miss rate for overall accesses
+system.cpu1.dcache.overall_mshr_miss_rate::total 0.041063 # mshr miss rate for overall accesses
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 12177.904592 # average ReadReq mshr miss latency
+system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 12177.904592 # average ReadReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 26814.418534 # average WriteReq mshr miss latency
+system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 26814.418534 # average WriteReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::cpu1.data 7953.694417 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.LoadLockedReq_avg_mshr_miss_latency::total 7953.694417 # average LoadLockedReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::cpu1.data 5338.766742 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.StoreCondReq_avg_mshr_miss_latency::total 5338.766742 # average StoreCondReq mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
+system.cpu1.dcache.demand_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 17038.535579 # average overall mshr miss latency
+system.cpu1.dcache.overall_avg_mshr_miss_latency::total 17038.535579 # average overall mshr miss latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::cpu1.data inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu1.dcache.WriteReq_avg_mshr_uncacheable_latency::cpu1.data inf # average WriteReq mshr uncacheable latency
system.cpu1.dcache.overall_avg_mshr_uncacheable_latency::total inf # average overall mshr uncacheable latency
system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
-system.cpu0.kern.inst.quiesce 6612 # number of quiesce instructions executed
-system.cpu0.kern.inst.hwrei 175930 # number of hwrei instructions executed
-system.cpu0.kern.ipl_count::0 61741 40.36% 40.36% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::21 135 0.09% 40.45% # number of times we switched to this ipl
+system.cpu0.kern.inst.quiesce 6610 # number of quiesce instructions executed
+system.cpu0.kern.inst.hwrei 175912 # number of hwrei instructions executed
+system.cpu0.kern.ipl_count::0 61740 40.36% 40.36% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::21 131 0.09% 40.45% # number of times we switched to this ipl
system.cpu0.kern.ipl_count::22 1928 1.26% 41.71% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::30 255 0.17% 41.87% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::31 88920 58.13% 100.00% # number of times we switched to this ipl
-system.cpu0.kern.ipl_count::total 152979 # number of times we switched to this ipl
-system.cpu0.kern.ipl_good::0 60877 49.17% 49.17% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::21 135 0.11% 49.28% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_count::30 255 0.17% 41.88% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::31 88907 58.12% 100.00% # number of times we switched to this ipl
+system.cpu0.kern.ipl_count::total 152961 # number of times we switched to this ipl
+system.cpu0.kern.ipl_good::0 60876 49.17% 49.17% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::21 131 0.11% 49.27% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::22 1928 1.56% 50.83% # number of times we switched to this ipl from a different ipl
system.cpu0.kern.ipl_good::30 255 0.21% 51.04% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::31 60624 48.96% 100.00% # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_good::total 123819 # number of times we switched to this ipl from a different ipl
-system.cpu0.kern.ipl_ticks::0 1865666624000 98.16% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::21 63262500 0.00% 98.16% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::22 564029000 0.03% 98.19% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::30 124022000 0.01% 98.19% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::31 34308226500 1.81% 100.00% # number of cycles we spent at this ipl
-system.cpu0.kern.ipl_ticks::total 1900726164000 # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_good::31 60621 48.96% 100.00% # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_good::total 123811 # number of times we switched to this ipl from a different ipl
+system.cpu0.kern.ipl_ticks::0 1865672058500 98.16% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::21 62377000 0.00% 98.16% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::22 564179500 0.03% 98.19% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::30 124028500 0.01% 98.20% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::31 34304214500 1.80% 100.00% # number of cycles we spent at this ipl
+system.cpu0.kern.ipl_ticks::total 1900726858000 # number of cycles we spent at this ipl
system.cpu0.kern.ipl_used::0 0.986006 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::21 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::31 0.681781 # fraction of swpipl calls that actually changed the ipl
-system.cpu0.kern.ipl_used::total 0.809386 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::31 0.681847 # fraction of swpipl calls that actually changed the ipl
+system.cpu0.kern.ipl_used::total 0.809429 # fraction of swpipl calls that actually changed the ipl
system.cpu0.kern.syscall::2 7 3.47% 3.47% # number of syscalls executed
system.cpu0.kern.syscall::3 16 7.92% 11.39% # number of syscalls executed
system.cpu0.kern.syscall::4 4 1.98% 13.37% # number of syscalls executed
system.cpu0.kern.callpal::wrmces 1 0.00% 0.22% # number of callpals executed
system.cpu0.kern.callpal::wrfen 1 0.00% 0.22% # number of callpals executed
system.cpu0.kern.callpal::wrvptptr 1 0.00% 0.23% # number of callpals executed
-system.cpu0.kern.callpal::swpctx 3342 2.07% 2.30% # number of callpals executed
+system.cpu0.kern.callpal::swpctx 3342 2.08% 2.30% # number of callpals executed
system.cpu0.kern.callpal::tbi 48 0.03% 2.33% # number of callpals executed
system.cpu0.kern.callpal::wrent 7 0.00% 2.33% # number of callpals executed
-system.cpu0.kern.callpal::swpipl 146235 90.79% 93.12% # number of callpals executed
+system.cpu0.kern.callpal::swpipl 146221 90.79% 93.12% # number of callpals executed
system.cpu0.kern.callpal::rdps 6169 3.83% 96.95% # number of callpals executed
system.cpu0.kern.callpal::wrkgp 1 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::wrusp 3 0.00% 96.95% # number of callpals executed
system.cpu0.kern.callpal::rdusp 8 0.00% 96.96% # number of callpals executed
system.cpu0.kern.callpal::whami 2 0.00% 96.96% # number of callpals executed
-system.cpu0.kern.callpal::rti 4427 2.75% 99.71% # number of callpals executed
+system.cpu0.kern.callpal::rti 4425 2.75% 99.71% # number of callpals executed
system.cpu0.kern.callpal::callsys 333 0.21% 99.91% # number of callpals executed
system.cpu0.kern.callpal::imb 137 0.09% 100.00% # number of callpals executed
-system.cpu0.kern.callpal::total 161075 # number of callpals executed
-system.cpu0.kern.mode_switch::kernel 6928 # number of protection mode switches
-system.cpu0.kern.mode_switch::user 1259 # number of protection mode switches
+system.cpu0.kern.callpal::total 161059 # number of callpals executed
+system.cpu0.kern.mode_switch::kernel 6926 # number of protection mode switches
+system.cpu0.kern.mode_switch::user 1257 # number of protection mode switches
system.cpu0.kern.mode_switch::idle 0 # number of protection mode switches
-system.cpu0.kern.mode_good::kernel 1258
-system.cpu0.kern.mode_good::user 1259
+system.cpu0.kern.mode_good::kernel 1256
+system.cpu0.kern.mode_good::user 1257
system.cpu0.kern.mode_good::idle 0
-system.cpu0.kern.mode_switch_good::kernel 0.181582 # fraction of useful protection mode switches
+system.cpu0.kern.mode_switch_good::kernel 0.181346 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu0.kern.mode_switch_good::idle nan # fraction of useful protection mode switches
-system.cpu0.kern.mode_switch_good::total 0.307439 # fraction of useful protection mode switches
-system.cpu0.kern.mode_ticks::kernel 1898815475500 99.90% 99.90% # number of ticks spent at the given mode
-system.cpu0.kern.mode_ticks::user 1910680500 0.10% 100.00% # number of ticks spent at the given mode
+system.cpu0.kern.mode_switch_good::total 0.307100 # fraction of useful protection mode switches
+system.cpu0.kern.mode_ticks::kernel 1898828643000 99.90% 99.90% # number of ticks spent at the given mode
+system.cpu0.kern.mode_ticks::user 1898207000 0.10% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.mode_ticks::idle 0 0.00% 100.00% # number of ticks spent at the given mode
system.cpu0.kern.swap_context 3343 # number of times the context was actually changed
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
-system.cpu1.kern.inst.quiesce 2522 # number of quiesce instructions executed
+system.cpu1.kern.inst.quiesce 2523 # number of quiesce instructions executed
system.cpu1.kern.inst.hwrei 64668 # number of hwrei instructions executed
system.cpu1.kern.ipl_count::0 20885 37.61% 37.61% # number of times we switched to this ipl
system.cpu1.kern.ipl_count::22 1927 3.47% 41.08% # number of times we switched to this ipl
system.cpu1.kern.ipl_good::30 359 0.84% 53.10% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::31 20014 46.90% 100.00% # number of times we switched to this ipl from a different ipl
system.cpu1.kern.ipl_good::total 42672 # number of times we switched to this ipl from a different ipl
-system.cpu1.kern.ipl_ticks::0 1875014442000 98.66% 98.66% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::22 532441000 0.03% 98.69% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::30 162321000 0.01% 98.70% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::31 24727641000 1.30% 100.00% # number of cycles we spent at this ipl
-system.cpu1.kern.ipl_ticks::total 1900436845000 # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::0 1875010715500 98.66% 98.66% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::22 532408500 0.03% 98.69% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::30 162327000 0.01% 98.70% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::31 24731034000 1.30% 100.00% # number of cycles we spent at this ipl
+system.cpu1.kern.ipl_ticks::total 1900436485000 # number of cycles we spent at this ipl
system.cpu1.kern.ipl_used::0 0.975437 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::22 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.ipl_used::30 1 # fraction of swpipl calls that actually changed the ipl
system.cpu1.kern.mode_switch_good::user 1 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::idle 0.110590 # fraction of useful protection mode switches
system.cpu1.kern.mode_switch_good::total 0.330476 # fraction of useful protection mode switches
-system.cpu1.kern.mode_ticks::kernel 5766448000 0.30% 0.30% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::user 831527500 0.04% 0.35% # number of ticks spent at the given mode
-system.cpu1.kern.mode_ticks::idle 1893827791500 99.65% 100.00% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::kernel 5768410500 0.30% 0.30% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::user 833727500 0.04% 0.35% # number of ticks spent at the given mode
+system.cpu1.kern.mode_ticks::idle 1893823776000 99.65% 100.00% # number of ticks spent at the given mode
system.cpu1.kern.swap_context 1394 # number of times the context was actually changed
---------- End Simulation Statistics ----------
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 01:26:55
+gem5 compiled Mar 28 2013 10:14:03
+gem5 started Mar 28 2013 10:14:28
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-checker
Global frequency set at 1000000000000 ticks per second
sim_ticks 2533114761500 # Number of ticks simulated
final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 19921 # Simulator instruction rate (inst/s)
-host_op_rate 25633 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 836738491 # Simulator tick rate (ticks/s)
-host_mem_usage 439300 # Number of bytes of host memory used
-host_seconds 3027.37 # Real time elapsed on the host
+host_inst_rate 40037 # Simulator instruction rate (inst/s)
+host_op_rate 51517 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1681683677 # Simulator tick rate (ticks/s)
+host_mem_usage 439348 # Number of bytes of host memory used
+host_seconds 1506.30 # Real time elapsed on the host
sim_insts 60307912 # Number of instructions simulated
sim_ops 77599507 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.cpu.int_regfile_writes 88426578 # number of integer regfile writes
system.cpu.fp_regfile_reads 8298 # number of floating regfile reads
system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30118912 # number of misc regfile reads
+system.cpu.misc_regfile_reads 30119271 # number of misc regfile reads
system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
system.cpu.icache.replacements 980182 # number of replacements
system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:41:12
+gem5 compiled Mar 28 2013 10:14:03
+gem5 started Mar 28 2013 10:17:38
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3-dual
Global frequency set at 1000000000000 ticks per second
sim_ticks 2602778916500 # Number of ticks simulated
final_tick 2602778916500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24161 # Simulator instruction rate (inst/s)
-host_op_rate 31106 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1001764915 # Simulator tick rate (ticks/s)
-host_mem_usage 444424 # Number of bytes of host memory used
-host_seconds 2598.19 # Real time elapsed on the host
+host_inst_rate 48820 # Simulator instruction rate (inst/s)
+host_op_rate 62855 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2024215186 # Simulator tick rate (ticks/s)
+host_mem_usage 443440 # Number of bytes of host memory used
+host_seconds 1285.82 # Real time elapsed on the host
sim_insts 62774383 # Number of instructions simulated
sim_ops 80820330 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu0.inst 64 # Number of bytes read from this memory
system.cpu0.int_regfile_writes 34592870 # number of integer regfile writes
system.cpu0.fp_regfile_reads 3226 # number of floating regfile reads
system.cpu0.fp_regfile_writes 898 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 13195358 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 13196303 # number of misc regfile reads
system.cpu0.misc_regfile_writes 457522 # number of misc regfile writes
system.cpu0.icache.replacements 399011 # number of replacements
system.cpu0.icache.tagsinuse 511.581015 # Cycle average of tags in use
system.cpu1.int_regfile_writes 57301820 # number of integer regfile writes
system.cpu1.fp_regfile_reads 4905 # number of floating regfile reads
system.cpu1.fp_regfile_writes 2316 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 18908919 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 18909839 # number of misc regfile reads
system.cpu1.misc_regfile_writes 419175 # number of misc regfile writes
system.cpu1.icache.replacements 613709 # number of replacements
system.cpu1.icache.tagsinuse 498.827741 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:43:56
+gem5 compiled Mar 28 2013 10:14:03
+gem5 started Mar 28 2013 10:15:55
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-o3
Global frequency set at 1000000000000 ticks per second
sim_ticks 2533114761500 # Number of ticks simulated
final_tick 2533114761500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24105 # Simulator instruction rate (inst/s)
-host_op_rate 31016 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1012479744 # Simulator tick rate (ticks/s)
-host_mem_usage 439308 # Number of bytes of host memory used
-host_seconds 2501.89 # Real time elapsed on the host
+host_inst_rate 48903 # Simulator instruction rate (inst/s)
+host_op_rate 62925 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2054075271 # Simulator tick rate (ticks/s)
+host_mem_usage 439344 # Number of bytes of host memory used
+host_seconds 1233.21 # Real time elapsed on the host
sim_insts 60307912 # Number of instructions simulated
sim_ops 77599507 # Number of ops (including micro ops) simulated
system.realview.nvmem.bytes_read::cpu.inst 64 # Number of bytes read from this memory
system.cpu.int_regfile_writes 88426576 # number of integer regfile writes
system.cpu.fp_regfile_reads 8298 # number of floating regfile reads
system.cpu.fp_regfile_writes 2914 # number of floating regfile writes
-system.cpu.misc_regfile_reads 30118912 # number of misc regfile reads
+system.cpu.misc_regfile_reads 30119271 # number of misc regfile reads
system.cpu.misc_regfile_writes 831902 # number of misc regfile writes
system.cpu.icache.replacements 980182 # number of replacements
system.cpu.icache.tagsinuse 511.616610 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:07:42
+gem5 compiled Mar 28 2013 10:14:03
+gem5 started Mar 28 2013 10:14:28
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-full
Global frequency set at 1000000000000 ticks per second
sim_ticks 2400708253000 # Number of ticks simulated
final_tick 2400708253000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 71724 # Simulator instruction rate (inst/s)
-host_op_rate 92116 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 2854182500 # Simulator tick rate (ticks/s)
-host_mem_usage 441348 # Number of bytes of host memory used
-host_seconds 841.12 # Real time elapsed on the host
+host_inst_rate 141448 # Simulator instruction rate (inst/s)
+host_op_rate 181662 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 5628731106 # Simulator tick rate (ticks/s)
+host_mem_usage 441396 # Number of bytes of host memory used
+host_seconds 426.51 # Real time elapsed on the host
sim_insts 60328852 # Number of instructions simulated
sim_ops 77480507 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 114819072 # Number of bytes read from this memory
system.cpu2.int_regfile_writes 29255277 # number of integer regfile writes
system.cpu2.fp_regfile_reads 22374 # number of floating regfile reads
system.cpu2.fp_regfile_writes 20830 # number of floating regfile writes
-system.cpu2.misc_regfile_reads 9021581 # number of misc regfile reads
+system.cpu2.misc_regfile_reads 9021591 # number of misc regfile reads
system.cpu2.misc_regfile_writes 240632 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:15:23
-gem5 started Mar 27 2013 02:19:45
+gem5 compiled Mar 28 2013 10:14:03
+gem5 started Mar 28 2013 10:14:28
gem5 executing on ribera.cs.wisc.edu
command line: build/ARM/gem5.opt -d build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3 -re tests/run.py build/ARM/tests/opt/long/fs/10.linux-boot/arm/linux/realview-switcheroo-o3
Global frequency set at 1000000000000 ticks per second
sim_ticks 2543226083000 # Number of ticks simulated
final_tick 2543226083000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 24298 # Simulator instruction rate (inst/s)
-host_op_rate 31265 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 1024641665 # Simulator tick rate (ticks/s)
-host_mem_usage 442376 # Number of bytes of host memory used
-host_seconds 2482.06 # Real time elapsed on the host
+host_inst_rate 48764 # Simulator instruction rate (inst/s)
+host_op_rate 62745 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 2056325427 # Simulator tick rate (ticks/s)
+host_mem_usage 443444 # Number of bytes of host memory used
+host_seconds 1236.78 # Real time elapsed on the host
sim_insts 60309820 # Number of instructions simulated
sim_ops 77602107 # Number of ops (including micro ops) simulated
system.physmem.bytes_read::realview.clcd 121110528 # Number of bytes read from this memory
system.cpu0.int_regfile_writes 45811922 # number of integer regfile writes
system.cpu0.fp_regfile_reads 22666 # number of floating regfile reads
system.cpu0.fp_regfile_writes 19880 # number of floating regfile writes
-system.cpu0.misc_regfile_reads 15681131 # number of misc regfile reads
+system.cpu0.misc_regfile_reads 15681354 # number of misc regfile reads
system.cpu0.misc_regfile_writes 434463 # number of misc regfile writes
system.cpu0.icache.replacements 984470 # number of replacements
system.cpu0.icache.tagsinuse 511.608417 # Cycle average of tags in use
system.cpu1.int_regfile_writes 42457075 # number of integer regfile writes
system.cpu1.fp_regfile_reads 22098 # number of floating regfile reads
system.cpu1.fp_regfile_writes 19630 # number of floating regfile writes
-system.cpu1.misc_regfile_reads 14600078 # number of misc regfile reads
+system.cpu1.misc_regfile_reads 14600215 # number of misc regfile reads
system.cpu1.misc_regfile_writes 398004 # number of misc regfile writes
system.iocache.replacements 0 # number of replacements
system.iocache.tagsinuse 0 # Cycle average of tags in use
[system.e820_table]
type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
+children=entries0 entries1 entries2
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
[system.e820_table.entries0]
type=X86E820Entry
addr=0
-range_type=2
-size=1048576
+range_type=1
+size=654336
[system.e820_table.entries1]
type=X86E820Entry
+addr=654336
+range_type=2
+size=394240
+
+[system.e820_table.entries2]
+type=X86E820Entry
addr=1048576
range_type=1
size=133169152
warn: Don't know what interrupt to clear for console.
warn: x86 cpuid: unknown family 0xbacc
warn: x86 cpuid: unknown family 0xbacc
-warn: x86 cpuid: unknown family 0xbacc
warn: instruction 'fxsave' unimplemented
warn: x86 cpuid: unknown family 0x8086
warn: x86 cpuid: unknown family 0x8086
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Mar 26 2013 15:13:59
-gem5 started Mar 27 2013 00:32:51
+gem5 compiled Mar 28 2013 09:59:18
+gem5 started Mar 28 2013 09:59:39
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing -re tests/run.py build/X86/tests/opt/long/fs/10.linux-boot/x86/linux/pc-o3-timing
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5132865528000 because m5_exit instruction encountered
+Exiting @ tick 5132969930500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.132866 # Number of seconds simulated
-sim_ticks 5132865528000 # Number of ticks simulated
-final_tick 5132865528000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.132970 # Number of seconds simulated
+sim_ticks 5132969930500 # Number of ticks simulated
+final_tick 5132969930500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 61482 # Simulator instruction rate (inst/s)
-host_op_rate 121532 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 773550742 # Simulator tick rate (ticks/s)
-host_mem_usage 771808 # Number of bytes of host memory used
-host_seconds 6635.46 # Real time elapsed on the host
-sim_insts 407963797 # Number of instructions simulated
-sim_ops 806422961 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2435200 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 3328 # Number of bytes read from this memory
+host_inst_rate 124251 # Simulator instruction rate (inst/s)
+host_op_rate 245606 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 1563205434 # Simulator tick rate (ticks/s)
+host_mem_usage 769808 # Number of bytes of host memory used
+host_seconds 3283.62 # Real time elapsed on the host
+sim_insts 407992820 # Number of instructions simulated
+sim_ops 806477449 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2455424 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.dtb.walker 2880 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 384 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 1080768 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10867584 # Number of bytes read from this memory
-system.physmem.bytes_read::total 14387264 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 1080768 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1080768 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9583040 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9583040 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38050 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 52 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 1078336 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10828544 # Number of bytes read from this memory
+system.physmem.bytes_read::total 14365568 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 1078336 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1078336 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9561728 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9561728 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 38366 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.dtb.walker 45 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 6 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 16887 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 169806 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 224801 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 149735 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 149735 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 474433 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 648 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 16849 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 169196 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 224462 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 149402 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 149402 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 478363 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.dtb.walker 561 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 75 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 210558 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2117255 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2802969 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 210558 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 210558 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1866996 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1866996 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1866996 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 474433 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 648 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 210080 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2109606 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2798685 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 210080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 210080 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1862806 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1862806 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1862806 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 478363 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.dtb.walker 561 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 75 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 210558 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2117255 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4669965 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 224801 # Total number of read requests seen
-system.physmem.writeReqs 149735 # Total number of write requests seen
-system.physmem.cpureqs 378687 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 14387264 # Total number of bytes read from memory
-system.physmem.bytesWritten 9583040 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 14387264 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 9583040 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 88 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 4143 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 14181 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 13154 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 13072 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 16238 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 13617 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 13098 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 13611 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 16569 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 13873 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 13226 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 13363 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 15769 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 13267 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12663 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 13279 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 15733 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 9192 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 8646 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 8408 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 11578 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 8737 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 8467 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8901 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 11873 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 9014 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 8670 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 8751 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 11255 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 8399 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 8107 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 8591 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 11146 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 210080 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2109606 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4661492 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 224462 # Total number of read requests seen
+system.physmem.writeReqs 149402 # Total number of write requests seen
+system.physmem.cpureqs 377855 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 14365568 # Total number of bytes read from memory
+system.physmem.bytesWritten 9561728 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 14365568 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 9561728 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 117 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 3983 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 14085 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 13102 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 13279 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 16301 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 13529 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 13167 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 13352 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 16230 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 13914 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 13149 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 13590 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 15875 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 13170 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12525 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 13306 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 15771 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 9020 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 8543 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 8624 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 11619 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 8726 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 8620 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8763 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 11646 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 9037 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 8560 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 8885 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 11311 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 8333 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 8041 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 8600 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 11074 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 8 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5132865474500 # Total gap between requests
+system.physmem.totGap 5132969877000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 224801 # Categorize read packet sizes
+system.physmem.readPktSize::6 224462 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
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system.iocache.writebacks::total 46667 # number of writebacks
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.overall_mshr_miss_rate::total 1 # mshr miss rate for overall accesses
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-system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 162018.894028 # average WriteReq mshr miss latency
-system.iocache.WriteReq_avg_mshr_miss_latency::total 162018.894028 # average WriteReq mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
-system.iocache.demand_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 160919.875499 # average overall mshr miss latency
-system.iocache.overall_avg_mshr_miss_latency::total 160919.875499 # average overall mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::pc.south_bridge.ide 105179.854962 # average ReadReq mshr miss latency
+system.iocache.ReadReq_avg_mshr_miss_latency::total 105179.854962 # average ReadReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::pc.south_bridge.ide 160511.527461 # average WriteReq mshr miss latency
+system.iocache.WriteReq_avg_mshr_miss_latency::total 160511.527461 # average WriteReq mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
+system.iocache.demand_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::pc.south_bridge.ide 159446.406995 # average overall mshr miss latency
+system.iocache.overall_avg_mshr_miss_latency::total 159446.406995 # average overall mshr miss latency
system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
-system.pc.south_bridge.ide.disks0.dma_read_txs 32 # Number of DMA read transactions (not PRD).
+system.pc.south_bridge.ide.disks0.dma_read_txs 31 # Number of DMA read transactions (not PRD).
system.pc.south_bridge.ide.disks0.dma_write_full_pages 693 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_bytes 2985984 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks0.dma_write_txs 812 # Number of DMA write transactions.
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.branchPred.lookups 86256793 # Number of BP lookups
-system.cpu.branchPred.condPredicted 86256793 # Number of conditional branches predicted
-system.cpu.branchPred.condIncorrect 1113068 # Number of conditional branches incorrect
-system.cpu.branchPred.BTBLookups 81525739 # Number of BTB lookups
-system.cpu.branchPred.BTBHits 79259204 # Number of BTB hits
+system.cpu.branchPred.lookups 86228247 # Number of BP lookups
+system.cpu.branchPred.condPredicted 86228247 # Number of conditional branches predicted
+system.cpu.branchPred.condIncorrect 1109691 # Number of conditional branches incorrect
+system.cpu.branchPred.BTBLookups 81322722 # Number of BTB lookups
+system.cpu.branchPred.BTBHits 79235054 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
-system.cpu.branchPred.BTBHitPct 97.219853 # BTB Hit Percentage
+system.cpu.branchPred.BTBHitPct 97.432860 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 0 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
-system.cpu.numCycles 448546895 # number of cpu cycles simulated
+system.cpu.numCycles 448477988 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.fetch.icacheStallCycles 27629675 # Number of cycles fetch is stalled on an Icache miss
-system.cpu.fetch.Insts 426131263 # Number of instructions fetch has processed
-system.cpu.fetch.Branches 86256793 # Number of branches that fetch encountered
-system.cpu.fetch.predictedBranches 79259204 # Number of branches that fetch has predicted taken
-system.cpu.fetch.Cycles 163637829 # Number of cycles fetch has run and was not squashing or blocked
-system.cpu.fetch.SquashCycles 4743979 # Number of cycles fetch has spent squashing
-system.cpu.fetch.TlbCycles 122519 # Number of cycles fetch has spent waiting for tlb
-system.cpu.fetch.BlockedCycles 63152705 # Number of cycles fetch has spent blocked
-system.cpu.fetch.MiscStallCycles 36413 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
-system.cpu.fetch.PendingTrapStallCycles 51550 # Number of stall cycles due to pending traps
-system.cpu.fetch.IcacheWaitRetryStallCycles 359 # Number of stall cycles due to full MSHR
-system.cpu.fetch.CacheLines 9043434 # Number of cache lines fetched
-system.cpu.fetch.IcacheSquashes 488848 # Number of outstanding Icache misses that were squashed
-system.cpu.fetch.ItlbSquashes 3024 # Number of outstanding ITLB misses that were squashed
-system.cpu.fetch.rateDist::samples 258223805 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::mean 3.257780 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::stdev 3.417802 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.icacheStallCycles 27463696 # Number of cycles fetch is stalled on an Icache miss
+system.cpu.fetch.Insts 426083477 # Number of instructions fetch has processed
+system.cpu.fetch.Branches 86228247 # Number of branches that fetch encountered
+system.cpu.fetch.predictedBranches 79235054 # Number of branches that fetch has predicted taken
+system.cpu.fetch.Cycles 163617772 # Number of cycles fetch has run and was not squashing or blocked
+system.cpu.fetch.SquashCycles 4719624 # Number of cycles fetch has spent squashing
+system.cpu.fetch.TlbCycles 125826 # Number of cycles fetch has spent waiting for tlb
+system.cpu.fetch.BlockedCycles 63227537 # Number of cycles fetch has spent blocked
+system.cpu.fetch.MiscStallCycles 35895 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
+system.cpu.fetch.PendingTrapStallCycles 53383 # Number of stall cycles due to pending traps
+system.cpu.fetch.IcacheWaitRetryStallCycles 393 # Number of stall cycles due to full MSHR
+system.cpu.fetch.CacheLines 9034836 # Number of cache lines fetched
+system.cpu.fetch.IcacheSquashes 484573 # Number of outstanding Icache misses that were squashed
+system.cpu.fetch.ItlbSquashes 2662 # Number of outstanding ITLB misses that were squashed
+system.cpu.fetch.rateDist::samples 258095876 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::mean 3.259036 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::stdev 3.417947 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::0 95012138 36.79% 36.79% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::1 1565899 0.61% 37.40% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::2 71926197 27.85% 65.26% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::3 935616 0.36% 65.62% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::4 1604506 0.62% 66.24% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::5 2433567 0.94% 67.18% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::6 1079084 0.42% 67.60% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::7 1383528 0.54% 68.13% # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::8 82283270 31.87% 100.00% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::0 94906138 36.77% 36.77% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::1 1565225 0.61% 37.38% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::2 71916844 27.86% 65.24% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::3 940016 0.36% 65.61% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::4 1600383 0.62% 66.23% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::5 2424857 0.94% 67.17% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::6 1078498 0.42% 67.58% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::7 1383259 0.54% 68.12% # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.rateDist::8 82280656 31.88% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.rateDist::total 258223805 # Number of instructions fetched each cycle (Total)
-system.cpu.fetch.branchRate 0.192303 # Number of branch fetches per cycle
-system.cpu.fetch.rate 0.950026 # Number of inst fetches per cycle
-system.cpu.decode.IdleCycles 31307096 # Number of cycles decode is idle
-system.cpu.decode.BlockedCycles 60630076 # Number of cycles decode is blocked
-system.cpu.decode.RunCycles 159436775 # Number of cycles decode is running
-system.cpu.decode.UnblockCycles 3257103 # Number of cycles decode is unblocking
-system.cpu.decode.SquashCycles 3592755 # Number of cycles decode is squashing
-system.cpu.decode.DecodedInsts 838113616 # Number of instructions handled by decode
-system.cpu.decode.SquashedInsts 880 # Number of squashed instructions handled by decode
-system.cpu.rename.SquashCycles 3592755 # Number of cycles rename is squashing
-system.cpu.rename.IdleCycles 34040592 # Number of cycles rename is idle
-system.cpu.rename.BlockCycles 37476959 # Number of cycles rename is blocking
-system.cpu.rename.serializeStallCycles 11041434 # count of cycles rename stalled for serializing inst
-system.cpu.rename.RunCycles 159631550 # Number of cycles rename is running
-system.cpu.rename.UnblockCycles 12440515 # Number of cycles rename is unblocking
-system.cpu.rename.RenamedInsts 834468110 # Number of instructions processed by rename
-system.cpu.rename.ROBFullEvents 19385 # Number of times rename has blocked due to ROB full
-system.cpu.rename.IQFullEvents 5834152 # Number of times rename has blocked due to IQ full
-system.cpu.rename.LSQFullEvents 4771877 # Number of times rename has blocked due to LSQ full
-system.cpu.rename.FullRegisterEvents 8971 # Number of times there has been no free registers
-system.cpu.rename.RenamedOperands 996054249 # Number of destination operands rename has renamed
-system.cpu.rename.RenameLookups 1811560635 # Number of register rename lookups that rename has made
-system.cpu.rename.int_rename_lookups 1811560099 # Number of integer rename lookups
-system.cpu.rename.fp_rename_lookups 536 # Number of floating rename lookups
-system.cpu.rename.CommittedMaps 964410768 # Number of HB maps that are committed
-system.cpu.rename.UndoneMaps 31643474 # Number of HB maps that are undone due to squashing
-system.cpu.rename.serializingInsts 457361 # count of serializing insts renamed
-system.cpu.rename.tempSerializingInsts 464527 # count of temporary serializing insts renamed
-system.cpu.rename.skidInsts 28752334 # count of insts added to the skid buffer
-system.cpu.memDep0.insertedLoads 17095902 # Number of loads inserted to the mem dependence unit.
-system.cpu.memDep0.insertedStores 10132687 # Number of stores inserted to the mem dependence unit.
-system.cpu.memDep0.conflictingLoads 1166436 # Number of conflicting loads.
-system.cpu.memDep0.conflictingStores 902107 # Number of conflicting stores.
-system.cpu.iq.iqInstsAdded 828339786 # Number of instructions added to the IQ (excludes non-spec)
-system.cpu.iq.iqNonSpecInstsAdded 1247404 # Number of non-speculative instructions added to the IQ
-system.cpu.iq.iqInstsIssued 823331592 # Number of instructions issued
-system.cpu.iq.iqSquashedInstsIssued 149918 # Number of squashed instructions issued
-system.cpu.iq.iqSquashedInstsExamined 22245950 # Number of squashed instructions iterated over during squash; mainly for profiling
-system.cpu.iq.iqSquashedOperandsExamined 33811662 # Number of squashed operands that are examined and possibly removed from graph
-system.cpu.iq.iqSquashedNonSpecRemoved 194652 # Number of squashed non-spec instructions that were removed
-system.cpu.iq.issued_per_cycle::samples 258223805 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::mean 3.188442 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::stdev 2.385103 # Number of insts issued each cycle
+system.cpu.fetch.rateDist::total 258095876 # Number of instructions fetched each cycle (Total)
+system.cpu.fetch.branchRate 0.192269 # Number of branch fetches per cycle
+system.cpu.fetch.rate 0.950066 # Number of inst fetches per cycle
+system.cpu.decode.IdleCycles 31171664 # Number of cycles decode is idle
+system.cpu.decode.BlockedCycles 60678279 # Number of cycles decode is blocked
+system.cpu.decode.RunCycles 159406116 # Number of cycles decode is running
+system.cpu.decode.UnblockCycles 3268443 # Number of cycles decode is unblocking
+system.cpu.decode.SquashCycles 3571374 # Number of cycles decode is squashing
+system.cpu.decode.DecodedInsts 838032918 # Number of instructions handled by decode
+system.cpu.decode.SquashedInsts 987 # Number of squashed instructions handled by decode
+system.cpu.rename.SquashCycles 3571374 # Number of cycles rename is squashing
+system.cpu.rename.IdleCycles 33913667 # Number of cycles rename is idle
+system.cpu.rename.BlockCycles 37519467 # Number of cycles rename is blocking
+system.cpu.rename.serializeStallCycles 11021070 # count of cycles rename stalled for serializing inst
+system.cpu.rename.RunCycles 159605851 # Number of cycles rename is running
+system.cpu.rename.UnblockCycles 12464447 # Number of cycles rename is unblocking
+system.cpu.rename.RenamedInsts 834371126 # Number of instructions processed by rename
+system.cpu.rename.ROBFullEvents 19504 # Number of times rename has blocked due to ROB full
+system.cpu.rename.IQFullEvents 5869459 # Number of times rename has blocked due to IQ full
+system.cpu.rename.LSQFullEvents 4764277 # Number of times rename has blocked due to LSQ full
+system.cpu.rename.FullRegisterEvents 8601 # Number of times there has been no free registers
+system.cpu.rename.RenamedOperands 995955832 # Number of destination operands rename has renamed
+system.cpu.rename.RenameLookups 1811371309 # Number of register rename lookups that rename has made
+system.cpu.rename.int_rename_lookups 1811370333 # Number of integer rename lookups
+system.cpu.rename.fp_rename_lookups 976 # Number of floating rename lookups
+system.cpu.rename.CommittedMaps 964482413 # Number of HB maps that are committed
+system.cpu.rename.UndoneMaps 31473412 # Number of HB maps that are undone due to squashing
+system.cpu.rename.serializingInsts 459237 # count of serializing insts renamed
+system.cpu.rename.tempSerializingInsts 467213 # count of temporary serializing insts renamed
+system.cpu.rename.skidInsts 28827657 # count of insts added to the skid buffer
+system.cpu.memDep0.insertedLoads 17084902 # Number of loads inserted to the mem dependence unit.
+system.cpu.memDep0.insertedStores 10144761 # Number of stores inserted to the mem dependence unit.
+system.cpu.memDep0.conflictingLoads 1200685 # Number of conflicting loads.
+system.cpu.memDep0.conflictingStores 943086 # Number of conflicting stores.
+system.cpu.iq.iqInstsAdded 828239567 # Number of instructions added to the IQ (excludes non-spec)
+system.cpu.iq.iqNonSpecInstsAdded 1251844 # Number of non-speculative instructions added to the IQ
+system.cpu.iq.iqInstsIssued 823277169 # Number of instructions issued
+system.cpu.iq.iqSquashedInstsIssued 150176 # Number of squashed instructions issued
+system.cpu.iq.iqSquashedInstsExamined 22096824 # Number of squashed instructions iterated over during squash; mainly for profiling
+system.cpu.iq.iqSquashedOperandsExamined 33604785 # Number of squashed operands that are examined and possibly removed from graph
+system.cpu.iq.iqSquashedNonSpecRemoved 197691 # Number of squashed non-spec instructions that were removed
+system.cpu.iq.issued_per_cycle::samples 258095876 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::mean 3.189811 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::stdev 2.384487 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::0 71699549 27.77% 27.77% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::1 15529974 6.01% 33.78% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::2 10286408 3.98% 37.76% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::3 7471868 2.89% 40.66% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::4 75917572 29.40% 70.06% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::5 3857166 1.49% 71.55% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::6 72524361 28.09% 99.64% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::7 784342 0.30% 99.94% # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::8 152565 0.06% 100.00% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::0 71559419 27.73% 27.73% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::1 15540861 6.02% 33.75% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::2 10303423 3.99% 37.74% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::3 7474044 2.90% 40.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::4 75918752 29.41% 70.05% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::5 3850758 1.49% 71.54% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::6 72514611 28.10% 99.64% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::7 781198 0.30% 99.94% # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::8 152810 0.06% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
-system.cpu.iq.issued_per_cycle::total 258223805 # Number of insts issued each cycle
+system.cpu.iq.issued_per_cycle::total 258095876 # Number of insts issued each cycle
system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
-system.cpu.iq.fu_full::IntAlu 368681 34.39% 34.39% # attempts to use FU when none available
+system.cpu.iq.fu_full::IntAlu 369026 34.39% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntMult 0 0.00% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::IntDiv 0 0.00% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::FloatAdd 0 0.00% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 34.39% # attempts to use FU when none available
system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 34.39% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemRead 552933 51.58% 85.98% # attempts to use FU when none available
-system.cpu.iq.fu_full::MemWrite 150329 14.02% 100.00% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemRead 552435 51.48% 85.87% # attempts to use FU when none available
+system.cpu.iq.fu_full::MemWrite 151573 14.13% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
-system.cpu.iq.FU_type_0::No_OpClass 310005 0.04% 0.04% # Type of FU issued
-system.cpu.iq.FU_type_0::IntAlu 795767028 96.65% 96.69% # Type of FU issued
+system.cpu.iq.FU_type_0::No_OpClass 311214 0.04% 0.04% # Type of FU issued
+system.cpu.iq.FU_type_0::IntAlu 795705202 96.65% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::IntDiv 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::FloatAdd 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 96.69% # Type of FU issued
system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 96.69% # Type of FU issued
-system.cpu.iq.FU_type_0::MemRead 17865255 2.17% 98.86% # Type of FU issued
-system.cpu.iq.FU_type_0::MemWrite 9389304 1.14% 100.00% # Type of FU issued
+system.cpu.iq.FU_type_0::MemRead 17863780 2.17% 98.86% # Type of FU issued
+system.cpu.iq.FU_type_0::MemWrite 9396973 1.14% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
-system.cpu.iq.FU_type_0::total 823331592 # Type of FU issued
-system.cpu.iq.rate 1.835553 # Inst issue rate
-system.cpu.iq.fu_busy_cnt 1071943 # FU busy when requested
-system.cpu.iq.fu_busy_rate 0.001302 # FU busy rate (busy events/executed inst)
-system.cpu.iq.int_inst_queue_reads 1906239242 # Number of integer instruction queue reads
-system.cpu.iq.int_inst_queue_writes 851843261 # Number of integer instruction queue writes
-system.cpu.iq.int_inst_queue_wakeup_accesses 818849223 # Number of integer instruction queue wakeup accesses
-system.cpu.iq.fp_inst_queue_reads 219 # Number of floating instruction queue reads
-system.cpu.iq.fp_inst_queue_writes 250 # Number of floating instruction queue writes
-system.cpu.iq.fp_inst_queue_wakeup_accesses 54 # Number of floating instruction queue wakeup accesses
-system.cpu.iq.int_alu_accesses 824093432 # Number of integer alu accesses
-system.cpu.iq.fp_alu_accesses 98 # Number of floating point alu accesses
-system.cpu.iew.lsq.thread0.forwLoads 1643495 # Number of loads that had data forwarded from stores
+system.cpu.iq.FU_type_0::total 823277169 # Type of FU issued
+system.cpu.iq.rate 1.835714 # Inst issue rate
+system.cpu.iq.fu_busy_cnt 1073034 # FU busy when requested
+system.cpu.iq.fu_busy_rate 0.001303 # FU busy rate (busy events/executed inst)
+system.cpu.iq.int_inst_queue_reads 1906003583 # Number of integer instruction queue reads
+system.cpu.iq.int_inst_queue_writes 851598062 # Number of integer instruction queue writes
+system.cpu.iq.int_inst_queue_wakeup_accesses 818801577 # Number of integer instruction queue wakeup accesses
+system.cpu.iq.fp_inst_queue_reads 376 # Number of floating instruction queue reads
+system.cpu.iq.fp_inst_queue_writes 450 # Number of floating instruction queue writes
+system.cpu.iq.fp_inst_queue_wakeup_accesses 94 # Number of floating instruction queue wakeup accesses
+system.cpu.iq.int_alu_accesses 824038818 # Number of integer alu accesses
+system.cpu.iq.fp_alu_accesses 171 # Number of floating point alu accesses
+system.cpu.iew.lsq.thread0.forwLoads 1644527 # Number of loads that had data forwarded from stores
system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
-system.cpu.iew.lsq.thread0.squashedLoads 3116410 # Number of loads squashed
-system.cpu.iew.lsq.thread0.ignoredResponses 23570 # Number of memory responses ignored because the instruction is squashed
-system.cpu.iew.lsq.thread0.memOrderViolation 11612 # Number of memory ordering violations
-system.cpu.iew.lsq.thread0.squashedStores 1711798 # Number of stores squashed
+system.cpu.iew.lsq.thread0.squashedLoads 3094800 # Number of loads squashed
+system.cpu.iew.lsq.thread0.ignoredResponses 23435 # Number of memory responses ignored because the instruction is squashed
+system.cpu.iew.lsq.thread0.memOrderViolation 11502 # Number of memory ordering violations
+system.cpu.iew.lsq.thread0.squashedStores 1720038 # Number of stores squashed
system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
-system.cpu.iew.lsq.thread0.rescheduledLoads 1932508 # Number of loads that were rescheduled
-system.cpu.iew.lsq.thread0.cacheBlocked 11844 # Number of times an access to memory failed due to the cache being blocked
+system.cpu.iew.lsq.thread0.rescheduledLoads 1932547 # Number of loads that were rescheduled
+system.cpu.iew.lsq.thread0.cacheBlocked 11959 # Number of times an access to memory failed due to the cache being blocked
system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
-system.cpu.iew.iewSquashCycles 3592755 # Number of cycles IEW is squashing
-system.cpu.iew.iewBlockCycles 26248050 # Number of cycles IEW is blocking
-system.cpu.iew.iewUnblockCycles 2110636 # Number of cycles IEW is unblocking
-system.cpu.iew.iewDispatchedInsts 829587190 # Number of instructions dispatched to IQ
-system.cpu.iew.iewDispSquashedInsts 321004 # Number of squashed instructions skipped by dispatch
-system.cpu.iew.iewDispLoadInsts 17095902 # Number of dispatched load instructions
-system.cpu.iew.iewDispStoreInsts 10132687 # Number of dispatched store instructions
-system.cpu.iew.iewDispNonSpecInsts 717072 # Number of dispatched non-speculative instructions
-system.cpu.iew.iewIQFullEvents 1612321 # Number of times the IQ has become full, causing a stall
-system.cpu.iew.iewLSQFullEvents 11848 # Number of times the LSQ has become full, causing a stall
-system.cpu.iew.memOrderViolationEvents 11612 # Number of memory order violations
-system.cpu.iew.predictedTakenIncorrect 657039 # Number of branches that were predicted taken incorrectly
-system.cpu.iew.predictedNotTakenIncorrect 595254 # Number of branches that were predicted not taken incorrectly
-system.cpu.iew.branchMispredicts 1252293 # Number of branch mispredicts detected at execute
-system.cpu.iew.iewExecutedInsts 821445338 # Number of executed instructions
-system.cpu.iew.iewExecLoadInsts 17448687 # Number of load instructions executed
-system.cpu.iew.iewExecSquashedInsts 1886253 # Number of squashed instructions skipped in execute
+system.cpu.iew.iewSquashCycles 3571374 # Number of cycles IEW is squashing
+system.cpu.iew.iewBlockCycles 26260647 # Number of cycles IEW is blocking
+system.cpu.iew.iewUnblockCycles 2115726 # Number of cycles IEW is unblocking
+system.cpu.iew.iewDispatchedInsts 829491411 # Number of instructions dispatched to IQ
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+system.cpu.iew.iewDispStoreInsts 10144761 # Number of dispatched store instructions
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+system.cpu.iew.iewIQFullEvents 1617594 # Number of times the IQ has become full, causing a stall
+system.cpu.iew.iewLSQFullEvents 12405 # Number of times the LSQ has become full, causing a stall
+system.cpu.iew.memOrderViolationEvents 11502 # Number of memory order violations
+system.cpu.iew.predictedTakenIncorrect 654420 # Number of branches that were predicted taken incorrectly
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+system.cpu.iew.branchMispredicts 1246996 # Number of branch mispredicts detected at execute
+system.cpu.iew.iewExecutedInsts 821399469 # Number of executed instructions
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system.cpu.iew.exec_swp 0 # number of swp insts executed
system.cpu.iew.exec_nop 0 # number of nop insts executed
-system.cpu.iew.exec_refs 26607218 # number of memory reference insts executed
-system.cpu.iew.exec_branches 83228491 # Number of branches executed
-system.cpu.iew.exec_stores 9158531 # Number of stores executed
-system.cpu.iew.exec_rate 1.831348 # Inst execution rate
-system.cpu.iew.wb_sent 820983226 # cumulative count of insts sent to commit
-system.cpu.iew.wb_count 818849277 # cumulative count of insts written-back
-system.cpu.iew.wb_producers 639988645 # num instructions producing a value
-system.cpu.iew.wb_consumers 1045811759 # num instructions consuming a value
+system.cpu.iew.exec_refs 26617414 # number of memory reference insts executed
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+system.cpu.iew.wb_sent 820937084 # cumulative count of insts sent to commit
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system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
-system.cpu.iew.wb_rate 1.825560 # insts written-back per cycle
-system.cpu.iew.wb_fanout 0.611954 # average fanout of values written-back
+system.cpu.iew.wb_rate 1.825734 # insts written-back per cycle
+system.cpu.iew.wb_fanout 0.611920 # average fanout of values written-back
system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
-system.cpu.commit.commitSquashedInsts 23057499 # The number of squashed insts skipped by commit
-system.cpu.commit.commitNonSpecStalls 1052750 # The number of times commit has been forced to stall to communicate backwards
-system.cpu.commit.branchMispredicts 1117600 # The number of times a branch was mispredicted
-system.cpu.commit.committed_per_cycle::samples 254631050 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::mean 3.167025 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::stdev 2.854459 # Number of insts commited each cycle
+system.cpu.commit.commitSquashedInsts 22903910 # The number of squashed insts skipped by commit
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+system.cpu.commit.committed_per_cycle::mean 3.168565 # Number of insts commited each cycle
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system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::0 82837862 32.53% 32.53% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::1 11822724 4.64% 37.18% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::2 3905327 1.53% 38.71% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::3 74951929 29.44% 68.14% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::4 2438342 0.96% 69.10% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::5 1480698 0.58% 69.68% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::6 927919 0.36% 70.05% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::7 70920568 27.85% 97.90% # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::8 5345681 2.10% 100.00% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::0 82731188 32.50% 32.50% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::1 11811542 4.64% 37.14% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::2 3909670 1.54% 38.68% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::3 74949600 29.45% 68.13% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::4 2435927 0.96% 69.08% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::5 1480813 0.58% 69.67% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::6 938860 0.37% 70.04% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::7 70918382 27.86% 97.90% # Number of insts commited each cycle
+system.cpu.commit.committed_per_cycle::8 5348520 2.10% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
-system.cpu.commit.committed_per_cycle::total 254631050 # Number of insts commited each cycle
-system.cpu.commit.committedInsts 407963797 # Number of instructions committed
-system.cpu.commit.committedOps 806422961 # Number of ops (including micro ops) committed
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+system.cpu.commit.committedInsts 407992820 # Number of instructions committed
+system.cpu.commit.committedOps 806477449 # Number of ops (including micro ops) committed
system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
-system.cpu.commit.refs 22400378 # Number of memory references committed
-system.cpu.commit.loads 13979489 # Number of loads committed
-system.cpu.commit.membars 473507 # Number of memory barriers committed
-system.cpu.commit.branches 82198469 # Number of branches committed
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system.cpu.commit.fp_insts 0 # Number of committed floating point instructions.
-system.cpu.commit.int_insts 735362199 # Number of committed integer instructions.
+system.cpu.commit.int_insts 735419466 # Number of committed integer instructions.
system.cpu.commit.function_calls 0 # Number of function calls committed.
-system.cpu.commit.bw_lim_events 5345681 # number cycles where commit BW limit reached
+system.cpu.commit.bw_lim_events 5348520 # number cycles where commit BW limit reached
system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
-system.cpu.rob.rob_reads 1078687614 # The number of ROB reads
-system.cpu.rob.rob_writes 1662572605 # The number of ROB writes
-system.cpu.timesIdled 1222238 # Number of times that the entire CPU went into an idle state and unscheduled itself
-system.cpu.idleCycles 190323090 # Total number of cycles that the CPU has spent unscheduled due to idling
-system.cpu.quiesceCycles 9817181581 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
-system.cpu.committedInsts 407963797 # Number of Instructions Simulated
-system.cpu.committedOps 806422961 # Number of Ops (including micro ops) Simulated
-system.cpu.committedInsts_total 407963797 # Number of Instructions Simulated
-system.cpu.cpi 1.099477 # CPI: Cycles Per Instruction
-system.cpu.cpi_total 1.099477 # CPI: Total CPI of All Threads
-system.cpu.ipc 0.909523 # IPC: Instructions Per Cycle
-system.cpu.ipc_total 0.909523 # IPC: Total IPC of All Threads
-system.cpu.int_regfile_reads 1507059295 # number of integer regfile reads
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-system.cpu.misc_regfile_writes 402265 # number of misc regfile writes
-system.cpu.icache.replacements 1056074 # number of replacements
-system.cpu.icache.tagsinuse 510.395640 # Cycle average of tags in use
-system.cpu.icache.total_refs 7921465 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 1056586 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 7.497227 # Average number of references to valid blocks.
-system.cpu.icache.warmup_cycle 56044666000 # Cycle when the warmup percentage was hit.
-system.cpu.icache.occ_blocks::cpu.inst 510.395640 # Average occupied blocks per requestor
-system.cpu.icache.occ_percent::cpu.inst 0.996866 # Average percentage of cache occupancy
-system.cpu.icache.occ_percent::total 0.996866 # Average percentage of cache occupancy
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-system.cpu.icache.ReadReq_misses::total 1121968 # number of ReadReq misses
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-system.cpu.icache.demand_misses::total 1121968 # number of demand (read+write) misses
-system.cpu.icache.overall_misses::cpu.inst 1121968 # number of overall misses
-system.cpu.icache.overall_misses::total 1121968 # number of overall misses
-system.cpu.icache.ReadReq_miss_latency::cpu.inst 15396039491 # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_latency::total 15396039491 # number of ReadReq miss cycles
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-system.cpu.icache.overall_miss_latency::total 15396039491 # number of overall miss cycles
-system.cpu.icache.ReadReq_accesses::cpu.inst 9043433 # number of ReadReq accesses(hits+misses)
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-system.cpu.icache.overall_accesses::total 9043433 # number of overall (read+write) accesses
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-system.cpu.icache.overall_miss_rate::total 0.124064 # miss rate for overall accesses
-system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 13722.351699 # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_miss_latency::total 13722.351699 # average ReadReq miss latency
-system.cpu.icache.demand_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
-system.cpu.icache.demand_avg_miss_latency::total 13722.351699 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::cpu.inst 13722.351699 # average overall miss latency
-system.cpu.icache.overall_avg_miss_latency::total 13722.351699 # average overall miss latency
-system.cpu.icache.blocked_cycles::no_mshrs 11326 # number of cycles access was blocked
+system.cpu.rob.rob_reads 1078479140 # The number of ROB reads
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+system.cpu.timesIdled 1219186 # Number of times that the entire CPU went into an idle state and unscheduled itself
+system.cpu.idleCycles 190382112 # Total number of cycles that the CPU has spent unscheduled due to idling
+system.cpu.quiesceCycles 9817459293 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt
+system.cpu.committedInsts 407992820 # Number of Instructions Simulated
+system.cpu.committedOps 806477449 # Number of Ops (including micro ops) Simulated
+system.cpu.committedInsts_total 407992820 # Number of Instructions Simulated
+system.cpu.cpi 1.099230 # CPI: Cycles Per Instruction
+system.cpu.cpi_total 1.099230 # CPI: Total CPI of All Threads
+system.cpu.ipc 0.909728 # IPC: Instructions Per Cycle
+system.cpu.ipc_total 0.909728 # IPC: Total IPC of All Threads
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+system.cpu.icache.tagsinuse 510.337680 # Cycle average of tags in use
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+system.cpu.icache.occ_blocks::cpu.inst 510.337680 # Average occupied blocks per requestor
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+system.cpu.icache.overall_avg_miss_latency::cpu.inst 13727.327567 # average overall miss latency
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system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
-system.cpu.icache.blocked::no_mshrs 262 # number of cycles access was blocked
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system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
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system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
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-system.cpu.icache.overall_mshr_hits::total 62943 # number of overall MSHR hits
-system.cpu.icache.ReadReq_mshr_misses::cpu.inst 1059025 # number of ReadReq MSHR misses
-system.cpu.icache.ReadReq_mshr_misses::total 1059025 # number of ReadReq MSHR misses
-system.cpu.icache.demand_mshr_misses::cpu.inst 1059025 # number of demand (read+write) MSHR misses
-system.cpu.icache.demand_mshr_misses::total 1059025 # number of demand (read+write) MSHR misses
-system.cpu.icache.overall_mshr_misses::cpu.inst 1059025 # number of overall MSHR misses
-system.cpu.icache.overall_mshr_misses::total 1059025 # number of overall MSHR misses
-system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12680665992 # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_latency::total 12680665992 # number of ReadReq MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12680665992 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_latency::total 12680665992 # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12680665992 # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_latency::total 12680665992 # number of overall MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_miss_rate::total 0.117104 # mshr miss rate for ReadReq accesses
-system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_miss_rate::total 0.117104 # mshr miss rate for demand accesses
-system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.117104 # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_miss_rate::total 0.117104 # mshr miss rate for overall accesses
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-system.cpu.dtb_walker_cache.overall_avg_miss_latency::cpu.dtb.walker 12500.883889 # average overall miss latency
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-system.cpu.dtb_walker_cache.overall_mshr_miss_latency::total 1193971500 # number of overall MSHR miss cycles
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system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
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-system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000739 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.015983 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102921 # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_miss_rate::total 0.066340 # mshr miss rate for overall accesses
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56978.461242 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55813.741077 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 56197.474408 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10258.108122 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10258.108122 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39528.387833 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39528.387833 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 75308.653846 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 52375.833333 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56978.461242 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 43047.583685 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44310.166528 # average overall mshr miss latency
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.916070 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.916070 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.462406 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.462406 # mshr miss rate for ReadExReq accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_miss_rate::total 0.066316 # mshr miss rate for demand accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.dtb.walker 0.000432 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.itb.walker 0.000717 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016085 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.102465 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::total 0.066316 # mshr miss rate for overall accesses
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 55745.876551 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 55571.771535 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 55658.049036 # average ReadReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10272.484775 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10272.484775 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39403.921676 # average ReadExReq mshr miss latency
+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39403.921676 # average ReadExReq mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 83578.733333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 128125.833333 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55745.876551 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42896.616660 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 44066.654783 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
init_param=0
intel_mp_pointer=system.intel_mp_pointer
intel_mp_table=system.intel_mp_table
-kernel=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
+kernel=/scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
load_addr_mask=18446744073709551615
mem_mode=timing
mem_ranges=0:134217727
[system.e820_table]
type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
+children=entries0 entries1 entries2
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
[system.e820_table.entries0]
type=X86E820Entry
addr=0
-range_type=2
-size=1048576
+range_type=1
+size=654336
[system.e820_table.entries1]
type=X86E820Entry
+addr=654336
+range_type=2
+size=394240
+
+[system.e820_table.entries2]
+type=X86E820Entry
addr=1048576
range_type=1
size=133169152
[system.pc.south_bridge.ide.disks0.image.child]
type=RawDiskImage
-image_file=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/disks/linux-x86.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-x86.img
read_only=true
[system.pc.south_bridge.ide.disks1]
[system.pc.south_bridge.ide.disks1.image.child]
type=RawDiskImage
-image_file=/panfs/panasas-01.cs.wisc.edu/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
+image_file=/scratch/nilay/GEM5/system/disks/linux-bigswap2.img
read_only=true
[system.pc.south_bridge.int_lines0]
-Real time: Feb/02/2013 09:14:12
+Real time: Mar/28/2013 10:19:36
Profiler Stats
--------------
-Elapsed_time_in_seconds: 436
-Elapsed_time_in_minutes: 7.26667
-Elapsed_time_in_hours: 0.121111
-Elapsed_time_in_days: 0.0050463
+Elapsed_time_in_seconds: 824
+Elapsed_time_in_minutes: 13.7333
+Elapsed_time_in_hours: 0.228889
+Elapsed_time_in_days: 0.00953704
-Virtual_time_in_seconds: 433.18
-Virtual_time_in_minutes: 7.21967
-Virtual_time_in_hours: 0.120328
-Virtual_time_in_days: 0.00501366
+Virtual_time_in_seconds: 785.96
+Virtual_time_in_minutes: 13.0993
+Virtual_time_in_hours: 0.218322
+Virtual_time_in_days: 0.00909676
-Ruby_current_time: 10409965061
+Ruby_current_time: 10416271238
Ruby_start_time: 0
-Ruby_cycles: 10409965061
+Ruby_cycles: 10416271238
-mbytes_resident: 588.68
-mbytes_total: 829.668
-resident_ratio: 0.709551
+mbytes_resident: 597.965
+mbytes_total: 848.508
+resident_ratio: 0.704734
-ruby_cycles_executed: [ 10409965062 10409965062 ]
+ruby_cycles_executed: [ 10416271239 10416271239 ]
Busy Controller Counts:
L1Cache-0:0 L1Cache-1:0
Busy Bank Count:0
-sequencer_requests_outstanding: [binsize: 1 max: 2 count: 154388627 average: 1.00012 | standard deviation: 0.0108509 | 0 154370447 18180 ]
+sequencer_requests_outstanding: [binsize: 1 max: 2 count: 151895075 average: 1.00011 | standard deviation: 0.0104983 | 0 151878333 16742 ]
All Non-Zero Cycle Demand Cache Accesses
----------------------------------------
-miss_latency: [binsize: 2 max: 263 count: 154388626 average: 3.45295 | standard deviation: 5.08093 | 0 151691060 0 0 0 0 0 0 0 932074 1700 1471491 1386 91484 1411 25274 359 175 10 52 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3366 5595 7267 9460 50995 170 509 87 93 127 5 22 5 6 11 7 11 5 8 21 3 15 7 8 14 12 467 4221 10035 17511 13265 42618 770 863 2296 301 820 9 29 31 16 29 22 21 60 9 34 12 15 39 13 22 17 19 28 73 118 136 139 258 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_LD: [binsize: 2 max: 216 count: 15287660 average: 5.10329 | standard deviation: 8.51802 | 0 13851030 0 0 0 0 0 0 0 114273 254 1245086 851 32917 901 11066 297 137 7 51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 906 733 2346 2626 1955 53 89 31 23 28 1 1 1 1 2 2 3 2 5 2 1 2 5 1 0 5 0 1358 2851 4652 6044 5789 287 265 232 122 109 1 14 3 7 5 8 8 4 4 4 6 2 4 7 8 4 4 7 24 17 51 40 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST: [binsize: 2 max: 263 count: 9717541 average: 5.12153 | standard deviation: 15.1014 | 0 9364158 0 0 0 0 0 0 0 26589 30 173008 277 26750 293 2179 37 9 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 752 3237 3695 6369 48930 84 395 41 60 99 4 19 3 1 9 4 7 2 1 19 2 12 0 4 12 4 465 856 2775 8650 6848 36461 339 481 1953 169 701 7 12 27 7 23 5 9 52 3 25 2 11 33 5 12 6 12 17 15 67 61 98 232 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH: [binsize: 2 max: 212 count: 128176357 average: 3.11389 | standard deviation: 1.98121 | 0 127382579 0 0 0 0 0 0 0 775132 1367 1483 160 160 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1608 1524 785 35 36 16 21 9 3 0 0 2 1 4 0 1 1 1 2 0 0 1 1 3 1 2 2 1994 4324 4157 217 167 139 103 109 1 7 1 3 0 2 1 9 4 4 1 5 4 2 2 1 2 7 3 4 34 34 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read: [binsize: 2 max: 214 count: 522204 average: 6.16903 | standard deviation: 9.47337 | 0 450068 0 0 0 0 0 0 0 10580 41 32976 18 17714 78 9308 10 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 84 382 378 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 66 17 117 166 2 10 2 9 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 342432 average: 5.6474 | standard deviation: 7.89999 | 0 300793 0 0 0 0 0 0 0 5500 8 18938 80 13943 92 2721 15 19 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 52 22 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 19 35 39 35 3 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 342432 average: 3 | standard deviation: 0 | 0 0 0 342432 ]
-miss_latency_NULL: [binsize: 2 max: 263 count: 154388626 average: 3.45295 | standard deviation: 5.08093 | 0 151691060 0 0 0 0 0 0 0 932074 1700 1471491 1386 91484 1411 25274 359 175 10 52 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3366 5595 7267 9460 50995 170 509 87 93 127 5 22 5 6 11 7 11 5 8 21 3 15 7 8 14 12 467 4221 10035 17511 13265 42618 770 863 2296 301 820 9 29 31 16 29 22 21 60 9 34 12 15 39 13 22 17 19 28 73 118 136 139 258 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_LD: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ]
+miss_latency_NULL: [binsize: 2 max: 270 count: 151895074 average: 3.45632 | standard deviation: 5.15571 | 0 149239942 0 0 0 0 0 0 0 967471 601 1437653 515 54191 578 16215 159 100 5 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3728 6095 8851 10338 50892 181 524 114 95 129 11 19 5 10 11 7 17 11 13 20 10 22 6 8 20 12 460 4446 10447 18595 13927 42308 850 876 2239 314 825 19 13 50 26 40 9 27 54 19 22 11 23 46 13 18 16 21 30 78 155 130 157 221 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
imcomplete_dir_Times: 0
-miss_latency_LD_NULL: [binsize: 2 max: 216 count: 15287660 average: 5.10329 | standard deviation: 8.51802 | 0 13851030 0 0 0 0 0 0 0 114273 254 1245086 851 32917 901 11066 297 137 7 51 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 906 733 2346 2626 1955 53 89 31 23 28 1 1 1 1 2 2 3 2 5 2 1 2 5 1 0 5 0 1358 2851 4652 6044 5789 287 265 232 122 109 1 14 3 7 5 8 8 4 4 4 6 2 4 7 8 4 4 7 24 17 51 40 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_ST_NULL: [binsize: 2 max: 263 count: 9717541 average: 5.12153 | standard deviation: 15.1014 | 0 9364158 0 0 0 0 0 0 0 26589 30 173008 277 26750 293 2179 37 9 2 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 752 3237 3695 6369 48930 84 395 41 60 99 4 19 3 1 9 4 7 2 1 19 2 12 0 4 12 4 465 856 2775 8650 6848 36461 339 481 1953 169 701 7 12 27 7 23 5 9 52 3 25 2 11 33 5 12 6 12 17 15 67 61 98 232 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_IFETCH_NULL: [binsize: 2 max: 212 count: 128176357 average: 3.11389 | standard deviation: 1.98121 | 0 127382579 0 0 0 0 0 0 0 775132 1367 1483 160 160 47 0 0 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1608 1524 785 35 36 16 21 9 3 0 0 2 1 4 0 1 1 1 2 0 0 1 1 3 1 2 2 1994 4324 4157 217 167 139 103 109 1 7 1 3 0 2 1 9 4 4 1 5 4 2 2 1 2 7 3 4 34 34 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 522204 average: 6.16903 | standard deviation: 9.47337 | 0 450068 0 0 0 0 0 0 0 10580 41 32976 18 17714 78 9308 10 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 77 84 382 378 52 13 4 6 6 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 9 66 17 117 166 2 10 2 9 2 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 216 count: 342432 average: 5.6474 | standard deviation: 7.89999 | 0 300793 0 0 0 0 0 0 0 5500 8 18938 80 13943 92 2721 15 19 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 17 59 52 22 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 19 35 39 35 3 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
-miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 342432 average: 3 | standard deviation: 0 | 0 0 0 342432 ]
+miss_latency_LD_NULL: [binsize: 2 max: 218 count: 14874061 average: 5.10543 | standard deviation: 8.68005 | 0 13485161 0 0 0 0 0 0 0 129669 71 1200389 321 19342 354 4658 120 69 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 946 797 3688 3455 2377 59 103 45 35 24 6 0 1 3 5 3 8 4 3 2 5 4 5 2 7 3 3 1340 2962 4560 6434 5662 323 275 230 120 126 7 4 3 16 9 3 17 8 8 3 7 7 6 3 3 5 5 12 23 21 44 49 12 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_ST_NULL: [binsize: 2 max: 270 count: 9471875 average: 5.1858 | standard deviation: 15.4023 | 0 9121731 0 0 0 0 0 0 0 27134 22 181251 122 14247 125 1633 27 16 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 780 3347 3709 6401 48396 97 398 53 53 99 4 17 4 4 4 3 7 5 7 15 3 18 1 5 10 6 457 1055 3050 9771 7123 36234 361 508 1904 182 686 8 8 45 4 27 3 7 43 7 17 3 13 40 5 12 5 11 15 22 105 69 105 209 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_IFETCH_NULL: [binsize: 2 max: 213 count: 126380154 average: 3.11846 | standard deviation: 2.02437 | 0 125567964 0 0 0 0 0 0 0 794781 477 434 39 45 17 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1899 1850 989 40 49 13 20 10 1 5 1 2 0 2 1 1 2 1 1 3 0 0 0 1 2 2 0 2035 4358 4208 198 205 161 86 103 7 4 4 1 2 6 4 3 3 3 4 1 1 2 0 5 2 6 5 2 33 28 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_RMW_Read_NULL: [binsize: 2 max: 214 count: 490994 average: 6.03795 | standard deviation: 9.42736 | 0 425859 0 0 0 0 0 0 0 10420 25 32755 15 11997 35 8470 5 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 83 81 392 393 46 9 3 4 5 1 0 0 0 1 0 0 0 1 2 0 2 0 0 0 1 1 0 8 55 15 120 161 1 4 2 4 9 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Read_NULL: [binsize: 2 max: 212 count: 338995 average: 5.4473 | standard deviation: 7.76902 | 0 300232 0 0 0 0 0 0 0 5467 6 22824 18 8560 47 1454 7 6 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 20 20 73 49 24 3 0 2 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 22 41 52 46 4 3 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ]
+miss_latency_Locked_RMW_Write_NULL: [binsize: 1 max: 3 count: 338995 average: 3 | standard deviation: 0 | 0 0 0 338995 ]
All Non-Zero Cycle SW Prefetch Requests
------------------------------------
Message Delayed Cycles
----------------------
-Total_delay_cycles: [binsize: 1 max: 13 count: 11148256 average: 0.604022 | standard deviation: 1.43415 | 9463853 2800 1710 2621 1672785 2644 328 252 266 847 12 8 32 98 ]
- virtual_network_0_delay_cycles: [binsize: 1 max: 13 count: 6239603 average: 1.0483 | standard deviation: 1.76244 | 4605589 1196 497 650 1627478 2413 310 248 251 821 12 8 32 98 ]
- virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4783107 average: 0.0397315 | standard deviation: 0.393864 | 4733754 1343 974 1793 45008 175 18 4 15 23 ]
- virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 125546 average: 0.0221114 | standard deviation: 0.270483 | 124510 261 239 178 299 56 0 0 0 3 ]
+Total_delay_cycles: [binsize: 1 max: 19 count: 10868463 average: 0.59509 | standard deviation: 1.42425 | 9251200 1053 635 975 1612868 1042 121 110 109 275 4 9 9 51 0 0 1 0 0 1 ]
+ virtual_network_0_delay_cycles: [binsize: 1 max: 19 count: 6100210 average: 1.0435 | standard deviation: 1.75778 | 4509207 549 222 262 1588385 908 120 110 101 271 4 9 9 51 0 0 1 0 0 1 ]
+ virtual_network_1_delay_cycles: [binsize: 1 max: 9 count: 4687708 average: 0.0215679 | standard deviation: 0.291665 | 4661845 408 333 614 24389 107 1 0 8 3 ]
+ virtual_network_2_delay_cycles: [binsize: 1 max: 9 count: 80545 average: 0.0133217 | standard deviation: 0.21003 | 80148 96 80 99 94 27 0 0 0 1 ]
virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ]
Resource Usage
--------------
page_size: 4096
-user_time: 432
-system_time: 0
-page_reclaims: 142268
-page_faults: 18
+user_time: 784
+system_time: 1
+page_reclaims: 148403
+page_faults: 35
swaps: 0
-block_inputs: 28312
-block_outputs: 488
+block_inputs: 20600
+block_outputs: 736
Network Stats
-------------
-total_msg_count_Control: 8609139 68873112
-total_msg_count_Request_Control: 374943 2999544
-total_msg_count_Response_Data: 8904543 641127096
-total_msg_count_Response_Control: 11255934 90047472
-total_msg_count_Writeback_Data: 4892277 352243944
-total_msg_count_Writeback_Control: 242529 1940232
-total_msgs: 34279365 total_bytes: 1157231400
+total_msg_count_Control: 8498316 67986528
+total_msg_count_Request_Control: 239871 1918968
+total_msg_count_Response_Data: 8796423 633342456
+total_msg_count_Response_Control: 10879743 87037944
+total_msg_count_Writeback_Data: 4769004 343368288
+total_msg_count_Writeback_Control: 289518 2316144
+total_msgs: 33472875 total_bytes: 1135970328
switch_0_inlinks: 2
switch_0_outlinks: 2
-links_utilized_percent_switch_0: 0.0914404
- links_utilized_percent_switch_0_link_0: 0.0993566 bw: 16000 base_latency: 1
- links_utilized_percent_switch_0_link_1: 0.0835243 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_0_link_0_Request_Control: 66161 529288 [ 66161 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Data: 2118925 152562600 [ 0 2118925 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_0_Response_Control: 1549490 12395920 [ 0 1549490 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Control: 2137842 17102736 [ 2137842 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Response_Data: 60657 4367304 [ 0 60657 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Response_Control: 1598105 12784840 [ 0 28048 1570057 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Data: 1449700 104378400 [ 1449590 110 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_0_link_1_Writeback_Control: 60538 484304 [ 60538 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_0: 0.0315382
+ links_utilized_percent_switch_0_link_0: 0.037253 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_0_link_1: 0.0258234 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_0_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Control: 817583 6540664 [ 817583 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Data: 39381 2835432 [ 0 39381 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Response_Control: 495523 3964184 [ 0 15983 479540 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Data: 408673 29424456 [ 408575 98 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_0_link_1_Writeback_Control: 34072 272576 [ 34072 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_1_inlinks: 2
switch_1_outlinks: 2
-links_utilized_percent_switch_1: 0.0196015
- links_utilized_percent_switch_1_link_0: 0.0247433 bw: 16000 base_latency: 1
- links_utilized_percent_switch_1_link_1: 0.0144596 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_1_link_0_Request_Control: 59385 475080 [ 59385 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Response_Data: 538648 38782656 [ 0 538648 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_0_Response_Control: 244326 1954608 [ 0 244326 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Control: 559724 4477792 [ 559724 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Data: 57458 4136976 [ 0 57458 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Response_Control: 283798 2270384 [ 0 23090 260708 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Data: 181059 13036248 [ 180839 220 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_1_link_1_Writeback_Control: 20305 162440 [ 20305 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_1: 0.0764968
+ links_utilized_percent_switch_1_link_0: 0.0852244 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_1_link_1: 0.0677692 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_1_link_0_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_0_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Control: 1837549 14700392 [ 1837549 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Data: 32554 2343888 [ 0 32554 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Response_Control: 1296124 10368992 [ 0 16536 1279588 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Data: 1180995 85031640 [ 1180869 126 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_1_link_1_Writeback_Control: 62434 499472 [ 62434 0 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_2_inlinks: 2
switch_2_outlinks: 2
-links_utilized_percent_switch_2: 0.114092
- links_utilized_percent_switch_2_link_0: 0.102531 bw: 16000 base_latency: 1
- links_utilized_percent_switch_2_link_1: 0.125652 bw: 16000 base_latency: 1
-
- outgoing_messages_switch_2_link_0_Control: 2697566 21580528 [ 2697566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Response_Data: 216184 15565248 [ 0 216184 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Response_Control: 1945969 15567752 [ 0 115204 1830765 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Data: 1630759 117414648 [ 1630429 330 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_0_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Request_Control: 123851 990808 [ 123851 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Data: 2677919 192810168 [ 0 2677919 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_2_link_1_Response_Control: 1763458 14107664 [ 0 1763458 0 0 0 0 0 0 0 0 ] base_latency: 1
+links_utilized_percent_switch_2: 0.112511
+ links_utilized_percent_switch_2_link_0: 0.0996306 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_2_link_1: 0.125392 bw: 16000 base_latency: 1
+
+ outgoing_messages_switch_2_link_0_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_0_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Request_Control: 78781 630248 [ 78781 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Data: 2682566 193144752 [ 0 2682566 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_2_link_1_Response_Control: 1722824 13782592 [ 0 1722824 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_3_inlinks: 2
switch_3_outlinks: 2
-links_utilized_percent_switch_3: 0.00646039
- links_utilized_percent_switch_3_link_0: 0.00496714 bw: 16000 base_latency: 1
- links_utilized_percent_switch_3_link_1: 0.00795363 bw: 16000 base_latency: 1
+links_utilized_percent_switch_3: 0.00665498
+ links_utilized_percent_switch_3_link_0: 0.00509748 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_3_link_1: 0.00821249 bw: 16000 base_latency: 1
- outgoing_messages_switch_3_link_0_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_0_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Response_Data: 172147 12394584 [ 0 172147 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_3_link_1_Response_Control: 106617 852936 [ 0 106617 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_0_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Data: 177640 12790080 [ 0 177640 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_3_link_1_Response_Control: 112110 896880 [ 0 112110 0 0 0 0 0 0 0 0 ] base_latency: 1
switch_4_inlinks: 2
switch_4_outlinks: 2
switch_5_inlinks: 5
switch_5_outlinks: 5
-links_utilized_percent_switch_5: 0.0463196
- links_utilized_percent_switch_5_link_0: 0.0993566 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_1: 0.0247433 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_2: 0.102531 bw: 16000 base_latency: 1
- links_utilized_percent_switch_5_link_3: 0.00496714 bw: 16000 base_latency: 1
+links_utilized_percent_switch_5: 0.0454411
+ links_utilized_percent_switch_5_link_0: 0.037253 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_1: 0.0852244 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_2: 0.0996306 bw: 16000 base_latency: 1
+ links_utilized_percent_switch_5_link_3: 0.00509748 bw: 16000 base_latency: 1
links_utilized_percent_switch_5_link_4: 0 bw: 16000 base_latency: 1
- outgoing_messages_switch_5_link_0_Request_Control: 66161 529288 [ 66161 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_0_Response_Data: 2118925 152562600 [ 0 2118925 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_0_Response_Control: 1549490 12395920 [ 0 1549490 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Request_Control: 59385 475080 [ 59385 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Response_Data: 538648 38782656 [ 0 538648 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_1_Response_Control: 244326 1954608 [ 0 244326 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Control: 2697566 21580528 [ 2697566 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Response_Data: 216184 15565248 [ 0 216184 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Response_Control: 1945969 15567752 [ 0 115204 1830765 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Writeback_Data: 1630759 117414648 [ 1630429 330 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_2_Writeback_Control: 80843 646744 [ 80843 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Control: 172147 1377176 [ 172147 0 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Response_Data: 94424 6798528 [ 0 94424 0 0 0 0 0 0 0 0 ] base_latency: 1
- outgoing_messages_switch_5_link_3_Response_Control: 12193 97544 [ 0 12193 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Request_Control: 41862 334896 [ 41862 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Data: 805815 58018680 [ 0 805815 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_0_Response_Control: 466550 3732400 [ 0 466550 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Request_Control: 38683 309464 [ 38683 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Data: 1828030 131618160 [ 0 1828030 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_1_Response_Control: 1263466 10107728 [ 0 1263466 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Control: 2655132 21241056 [ 2655132 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Response_Data: 201773 14527656 [ 0 201773 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Response_Control: 1880978 15047824 [ 0 121850 1759128 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Writeback_Data: 1589668 114456096 [ 1589444 224 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_2_Writeback_Control: 96506 772048 [ 96506 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Control: 177640 1421120 [ 177640 0 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Response_Data: 96523 6949656 [ 0 96523 0 0 0 0 0 0 0 0 ] base_latency: 1
+ outgoing_messages_switch_5_link_3_Response_Control: 15587 124696 [ 0 15587 0 0 0 0 0 0 0 0 ] base_latency: 1
Cache Stats: system.ruby.l1_cntrl0.L1IcacheMemory
- system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 519313
- system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 519313
+ system.ruby.l1_cntrl0.L1IcacheMemory_total_misses: 313126
+ system.ruby.l1_cntrl0.L1IcacheMemory_total_demand_misses: 313126
system.ruby.l1_cntrl0.L1IcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_total_hw_prefetches: 0
system.ruby.l1_cntrl0.L1IcacheMemory_request_type_IFETCH: 100%
- system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 519313 100%
+ system.ruby.l1_cntrl0.L1IcacheMemory_access_mode_type_Supervisor: 313126 100%
Cache Stats: system.ruby.l1_cntrl0.L1DcacheMemory
- system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 1618529
- system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 1618529
+ system.ruby.l1_cntrl0.L1DcacheMemory_total_misses: 504457
+ system.ruby.l1_cntrl0.L1DcacheMemory_total_demand_misses: 504457
system.ruby.l1_cntrl0.L1DcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl0.L1DcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl0.L1DcacheMemory_total_hw_prefetches: 0
- system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 80.1035%
- system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 19.8965%
+ system.ruby.l1_cntrl0.L1DcacheMemory_request_type_LD: 54.7331%
+ system.ruby.l1_cntrl0.L1DcacheMemory_request_type_ST: 45.2669%
- system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 1618529 100%
+ system.ruby.l1_cntrl0.L1DcacheMemory_access_mode_type_Supervisor: 504457 100%
--- L1Cache ---
- Event Counts -
-Load [11524819 3762841 ] 15287660
-Ifetch [108056158 20120206 ] 128176364
-Store [7679126 3245483 ] 10924609
-Inv [28158 23310 ] 51468
-L1_Replacement [2094939 513666 ] 2608605
-Fwd_GETX [15349 14692 ] 30041
-Fwd_GETS [22649 21383 ] 44032
-Fwd_GET_INSTR [5 0 ] 5
-Data [1528 1030 ] 2558
-Data_Exclusive [1226643 92927 ] 1319570
-DataS_fromL1 [21383 22654 ] 44037
-Data_all_Acks [869371 422037 ] 1291408
-Ack [18917 21076 ] 39993
-Ack_all [20445 22106 ] 42551
-WB_Ack [1510128 201144 ] 1711272
+Load [6004899 8869162 ] 14874061
+Ifetch [67402410 58977750 ] 126380160
+Store [5078812 5562047 ] 10640859
+Inv [16081 16662 ] 32743
+L1_Replacement [790678 1810849 ] 2601527
+Fwd_GETX [12181 11488 ] 23669
+Fwd_GETS [13596 10533 ] 24129
+Fwd_GET_INSTR [4 0 ] 4
+Data [367 1125 ] 1492
+Data_Exclusive [240655 1040298 ] 1280953
+DataS_fromL1 [10533 13600 ] 24133
+Data_all_Acks [554260 773007 ] 1327267
+Ack [11768 9519 ] 21287
+Ack_all [12135 10644 ] 22779
+WB_Ack [442647 1243303 ] 1685950
PF_Load [0 0 ] 0
PF_Ifetch [0 0 ] 0
PF_Store [0 0 ] 0
- Transitions -
-NP Load [1280962 125221 ] 1406183
-NP Ifetch [519202 274242 ] 793444
-NP Store [295799 115227 ] 411026
-NP Inv [6572 2932 ] 9504
+NP Load [267792 1102795 ] 1370587
+NP Ifetch [313000 498627 ] 811627
+NP Store [210910 210451 ] 421361
+NP Inv [5429 3933 ] 9362
NP L1_Replacement [0 0 ] 0
NP PF_Load [0 0 ] 0
NP PF_Ifetch [0 0 ] 0
NP PF_Store [0 0 ] 0
-I Load [15536 14911 ] 30447
-I Ifetch [111 223 ] 334
-I Store [7315 8824 ] 16139
+I Load [8313 10000 ] 18313
+I Ifetch [126 437 ] 563
+I Store [5674 5720 ] 11394
I Inv [0 0 ] 0
-I L1_Replacement [13898 11112 ] 25010
+I L1_Replacement [8682 8060 ] 16742
I PF_Load [0 0 ] 0
I PF_Ifetch [0 0 ] 0
I PF_Store [0 0 ] 0
-S Load [750748 485618 ] 1236366
-S Ifetch [107536840 19845739 ] 127382579
-S Store [18917 21076 ] 39993
-S Inv [21408 20030 ] 41438
-S L1_Replacement [570913 301410 ] 872323
+S Load [551889 484566 ] 1036455
+S Ifetch [67089280 58478684 ] 125567964
+S Store [11768 9519 ] 21287
+S Inv [10451 12551 ] 23002
+S L1_Replacement [339349 559486 ] 898835
S PF_Load [0 0 ] 0
S PF_Store [0 0 ] 0
-E Load [3053712 595313 ] 3649025
+E Load [1058703 2799902 ] 3858605
E Ifetch [0 0 ] 0
-E Store [120709 32416 ] 153125
-E Inv [68 128 ] 196
-E L1_Replacement [1104096 58890 ] 1162986
-E Fwd_GETX [187 209 ] 396
-E Fwd_GETS [1490 1115 ] 2605
-E Fwd_GET_INSTR [1 0 ] 1
+E Store [78784 87850 ] 166634
+E Inv [103 52 ] 155
+E L1_Replacement [160570 950900 ] 1111470
+E Fwd_GETX [228 182 ] 410
+E Fwd_GETS [848 1108 ] 1956
+E Fwd_GET_INSTR [0 0 ] 0
E PF_Load [0 0 ] 0
E PF_Store [0 0 ] 0
-M Load [6423861 2541778 ] 8965639
+M Load [4118202 4471899 ] 8590101
M Ifetch [0 0 ] 0
-M Store [7236386 3067940 ] 10304326
-M Inv [110 220 ] 330
-M L1_Replacement [406032 142254 ] 548286
-M Fwd_GETX [15162 14483 ] 29645
-M Fwd_GETS [21159 20268 ] 41427
+M Store [4771676 5248507 ] 10020183
+M Inv [98 126 ] 224
+M L1_Replacement [282077 292403 ] 574480
+M Fwd_GETX [11953 11306 ] 23259
+M Fwd_GETS [12747 9423 ] 22170
M Fwd_GET_INSTR [4 0 ] 4
M PF_Load [0 0 ] 0
M PF_Store [0 0 ] 0
IS Store [0 0 ] 0
IS Inv [0 0 ] 0
IS L1_Replacement [0 0 ] 0
-IS Data_Exclusive [1226643 92927 ] 1319570
-IS DataS_fromL1 [21383 22654 ] 44037
-IS Data_all_Acks [567785 299016 ] 866801
+IS Data_Exclusive [240655 1040298 ] 1280953
+IS DataS_fromL1 [10533 13600 ] 24133
+IS Data_all_Acks [338043 557961 ] 896004
IS PF_Load [0 0 ] 0
IS PF_Store [0 0 ] 0
IM Store [0 0 ] 0
IM Inv [0 0 ] 0
IM L1_Replacement [0 0 ] 0
-IM Data [1528 1030 ] 2558
-IM Data_all_Acks [301586 123021 ] 424607
+IM Data [367 1125 ] 1492
+IM Data_all_Acks [216217 215046 ] 431263
IM Ack [0 0 ] 0
IM PF_Load [0 0 ] 0
IM PF_Store [0 0 ] 0
SM Store [0 0 ] 0
SM Inv [0 0 ] 0
SM L1_Replacement [0 0 ] 0
-SM Ack [18917 21076 ] 39993
-SM Ack_all [20445 22106 ] 42551
+SM Ack [11768 9519 ] 21287
+SM Ack_all [12135 10644 ] 22779
SM PF_Load [0 0 ] 0
SM PF_Store [0 0 ] 0
IS_I PF_Store [0 0 ] 0
M_I Load [0 0 ] 0
-M_I Ifetch [5 2 ] 7
+M_I Ifetch [4 2 ] 6
M_I Store [0 0 ] 0
M_I Inv [0 0 ] 0
M_I L1_Replacement [0 0 ] 0
M_I Fwd_GETX [0 0 ] 0
-M_I Fwd_GETS [0 0 ] 0
+M_I Fwd_GETS [1 2 ] 3
M_I Fwd_GET_INSTR [0 0 ] 0
-M_I WB_Ack [1510128 201144 ] 1711272
+M_I WB_Ack [442646 1243301 ] 1685947
M_I PF_Load [0 0 ] 0
M_I PF_Store [0 0 ] 0
SINK_WB_ACK Store [0 0 ] 0
SINK_WB_ACK Inv [0 0 ] 0
SINK_WB_ACK L1_Replacement [0 0 ] 0
-SINK_WB_ACK WB_Ack [0 0 ] 0
+SINK_WB_ACK WB_Ack [1 2 ] 3
SINK_WB_ACK PF_Load [0 0 ] 0
SINK_WB_ACK PF_Store [0 0 ] 0
PF_IS_I Data_all_Acks [0 0 ] 0
Cache Stats: system.ruby.l1_cntrl1.L1IcacheMemory
- system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 274465
- system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 274465
+ system.ruby.l1_cntrl1.L1IcacheMemory_total_misses: 499064
+ system.ruby.l1_cntrl1.L1IcacheMemory_total_demand_misses: 499064
system.ruby.l1_cntrl1.L1IcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_total_hw_prefetches: 0
system.ruby.l1_cntrl1.L1IcacheMemory_request_type_IFETCH: 100%
- system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 274465 100%
+ system.ruby.l1_cntrl1.L1IcacheMemory_access_mode_type_Supervisor: 499064 100%
Cache Stats: system.ruby.l1_cntrl1.L1DcacheMemory
- system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 285259
- system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 285259
+ system.ruby.l1_cntrl1.L1DcacheMemory_total_misses: 1338485
+ system.ruby.l1_cntrl1.L1DcacheMemory_total_demand_misses: 1338485
system.ruby.l1_cntrl1.L1DcacheMemory_total_prefetches: 0
system.ruby.l1_cntrl1.L1DcacheMemory_total_sw_prefetches: 0
system.ruby.l1_cntrl1.L1DcacheMemory_total_hw_prefetches: 0
- system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 49.1245%
- system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 50.8755%
+ system.ruby.l1_cntrl1.L1DcacheMemory_request_type_LD: 83.1384%
+ system.ruby.l1_cntrl1.L1DcacheMemory_request_type_ST: 16.8616%
- system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 285259 100%
+ system.ruby.l1_cntrl1.L1DcacheMemory_access_mode_type_Supervisor: 1338485 100%
Cache Stats: system.ruby.l2_cntrl0.L2cacheMemory
- system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 246225
- system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 246225
+ system.ruby.l2_cntrl0.L2cacheMemory_total_misses: 225442
+ system.ruby.l2_cntrl0.L2cacheMemory_total_demand_misses: 225442
system.ruby.l2_cntrl0.L2cacheMemory_total_prefetches: 0
system.ruby.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0
system.ruby.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 30.3877%
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 6.26541%
- system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 63.3469%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETS: 25.7405%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GET_INSTR: 7.27238%
+ system.ruby.l2_cntrl0.L2cacheMemory_request_type_GETX: 66.9871%
- system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 246225 100%
+ system.ruby.l2_cntrl0.L2cacheMemory_access_mode_type_Supervisor: 225442 100%
--- L2Cache ---
- Event Counts -
-L1_GET_INSTR [793778 ] 793778
-L1_GETS [1436873 ] 1436873
-L1_GETX [427166 ] 427166
-L1_UPGRADE [39993 ] 39993
-L1_PUTX [1711272 ] 1711272
+L1_GET_INSTR [812190 ] 812190
+L1_GETS [1389132 ] 1389132
+L1_GETX [432758 ] 432758
+L1_UPGRADE [21287 ] 21287
+L1_PUTX [1685953 ] 1685953
L1_PUTX_old [0 ] 0
Fwd_L1_GETX [0 ] 0
Fwd_L1_GETS [0 ] 0
Fwd_L1_GET_INSTR [0 ] 0
-L2_Replacement [94211 ] 94211
-L2_Replacement_clean [12406 ] 12406
-Mem_Data [172147 ] 172147
-Mem_Ack [106617 ] 106617
-WB_Data [43745 ] 43745
-WB_Data_clean [622 ] 622
-Ack [1695 ] 1695
-Ack_all [6892 ] 6892
-Unblock [44037 ] 44037
+L2_Replacement [96407 ] 96407
+L2_Replacement_clean [15703 ] 15703
+Mem_Data [177640 ] 177640
+Mem_Ack [112110 ] 112110
+WB_Data [23855 ] 23855
+WB_Data_clean [502 ] 502
+Ack [1764 ] 1764
+Ack_all [7976 ] 7976
+Unblock [24133 ] 24133
Unblock_Cancel [0 ] 0
-Exclusive_Unblock [1786728 ] 1786728
+Exclusive_Unblock [1734995 ] 1734995
MEM_Inv [0 ] 0
- Transitions -
-NP L1_GET_INSTR [15422 ] 15422
-NP L1_GETS [30790 ] 30790
-NP L1_GETX [125935 ] 125935
+NP L1_GET_INSTR [16391 ] 16391
+NP L1_GETS [33901 ] 33901
+NP L1_GETX [127348 ] 127348
NP L1_PUTX [0 ] 0
NP L1_PUTX_old [0 ] 0
-SS L1_GET_INSTR [778102 ] 778102
-SS L1_GETS [73028 ] 73028
-SS L1_GETX [2798 ] 2798
-SS L1_UPGRADE [39993 ] 39993
-SS L1_PUTX [0 ] 0
+SS L1_GET_INSTR [795630 ] 795630
+SS L1_GETS [83818 ] 83818
+SS L1_GETX [1691 ] 1691
+SS L1_UPGRADE [21287 ] 21287
+SS L1_PUTX [3 ] 3
SS L1_PUTX_old [0 ] 0
-SS L2_Replacement [248 ] 248
-SS L2_Replacement_clean [6448 ] 6448
+SS L2_Replacement [258 ] 258
+SS L2_Replacement_clean [7563 ] 7563
SS MEM_Inv [0 ] 0
-M L1_GET_INSTR [249 ] 249
-M L1_GETS [1288780 ] 1288780
-M L1_GETX [268391 ] 268391
+M L1_GET_INSTR [165 ] 165
+M L1_GETS [1247052 ] 1247052
+M L1_GETX [280047 ] 280047
M L1_PUTX [0 ] 0
M L1_PUTX_old [0 ] 0
-M L2_Replacement [93815 ] 93815
-M L2_Replacement_clean [5580 ] 5580
+M L2_Replacement [95992 ] 95992
+M L2_Replacement_clean [7918 ] 7918
M MEM_Inv [0 ] 0
-MT L1_GET_INSTR [5 ] 5
-MT L1_GETS [44032 ] 44032
-MT L1_GETX [30041 ] 30041
-MT L1_PUTX [1711272 ] 1711272
+MT L1_GET_INSTR [4 ] 4
+MT L1_GETS [24129 ] 24129
+MT L1_GETX [23669 ] 23669
+MT L1_PUTX [1685947 ] 1685947
MT L1_PUTX_old [0 ] 0
-MT L2_Replacement [148 ] 148
-MT L2_Replacement_clean [378 ] 378
+MT L2_Replacement [157 ] 157
+MT L2_Replacement_clean [222 ] 222
MT MEM_Inv [0 ] 0
M_I L1_GET_INSTR [0 ] 0
M_I L1_UPGRADE [0 ] 0
M_I L1_PUTX [0 ] 0
M_I L1_PUTX_old [0 ] 0
-M_I Mem_Ack [106617 ] 106617
+M_I Mem_Ack [112110 ] 112110
M_I MEM_Inv [0 ] 0
MT_I L1_GET_INSTR [0 ] 0
MT_I L1_UPGRADE [0 ] 0
MT_I L1_PUTX [0 ] 0
MT_I L1_PUTX_old [0 ] 0
-MT_I WB_Data [117 ] 117
+MT_I WB_Data [108 ] 108
MT_I WB_Data_clean [0 ] 0
-MT_I Ack_all [31 ] 31
+MT_I Ack_all [49 ] 49
MT_I MEM_Inv [0 ] 0
MCT_I L1_GET_INSTR [0 ] 0
MCT_I L1_UPGRADE [0 ] 0
MCT_I L1_PUTX [0 ] 0
MCT_I L1_PUTX_old [0 ] 0
-MCT_I WB_Data [213 ] 213
+MCT_I WB_Data [116 ] 116
MCT_I WB_Data_clean [0 ] 0
-MCT_I Ack_all [165 ] 165
+MCT_I Ack_all [106 ] 106
I_I L1_GET_INSTR [0 ] 0
I_I L1_GETS [0 ] 0
I_I L1_UPGRADE [0 ] 0
I_I L1_PUTX [0 ] 0
I_I L1_PUTX_old [0 ] 0
-I_I Ack [1454 ] 1454
-I_I Ack_all [6448 ] 6448
+I_I Ack [1506 ] 1506
+I_I Ack_all [7563 ] 7563
S_I L1_GET_INSTR [0 ] 0
S_I L1_GETS [0 ] 0
S_I L1_UPGRADE [0 ] 0
S_I L1_PUTX [0 ] 0
S_I L1_PUTX_old [0 ] 0
-S_I Ack [241 ] 241
-S_I Ack_all [248 ] 248
+S_I Ack [258 ] 258
+S_I Ack_all [258 ] 258
S_I MEM_Inv [0 ] 0
ISS L1_GET_INSTR [0 ] 0
ISS L1_PUTX_old [0 ] 0
ISS L2_Replacement [0 ] 0
ISS L2_Replacement_clean [0 ] 0
-ISS Mem_Data [30790 ] 30790
+ISS Mem_Data [33901 ] 33901
ISS MEM_Inv [0 ] 0
IS L1_GET_INSTR [0 ] 0
IS L1_PUTX_old [0 ] 0
IS L2_Replacement [0 ] 0
IS L2_Replacement_clean [0 ] 0
-IS Mem_Data [15422 ] 15422
+IS Mem_Data [16391 ] 16391
IS MEM_Inv [0 ] 0
IM L1_GET_INSTR [0 ] 0
IM L1_PUTX_old [0 ] 0
IM L2_Replacement [0 ] 0
IM L2_Replacement_clean [0 ] 0
-IM Mem_Data [125935 ] 125935
+IM Mem_Data [127348 ] 127348
IM MEM_Inv [0 ] 0
SS_MB L1_GET_INSTR [0 ] 0
-SS_MB L1_GETS [194 ] 194
-SS_MB L1_GETX [0 ] 0
+SS_MB L1_GETS [186 ] 186
+SS_MB L1_GETX [1 ] 1
SS_MB L1_UPGRADE [0 ] 0
SS_MB L1_PUTX [0 ] 0
SS_MB L1_PUTX_old [0 ] 0
SS_MB L2_Replacement [0 ] 0
SS_MB L2_Replacement_clean [0 ] 0
SS_MB Unblock_Cancel [0 ] 0
-SS_MB Exclusive_Unblock [42791 ] 42791
+SS_MB Exclusive_Unblock [22978 ] 22978
SS_MB MEM_Inv [0 ] 0
MT_MB L1_GET_INSTR [0 ] 0
-MT_MB L1_GETS [49 ] 49
-MT_MB L1_GETX [1 ] 1
+MT_MB L1_GETS [46 ] 46
+MT_MB L1_GETX [2 ] 2
MT_MB L1_UPGRADE [0 ] 0
MT_MB L1_PUTX [0 ] 0
MT_MB L1_PUTX_old [0 ] 0
MT_MB L2_Replacement [0 ] 0
MT_MB L2_Replacement_clean [0 ] 0
MT_MB Unblock_Cancel [0 ] 0
-MT_MB Exclusive_Unblock [1743937 ] 1743937
+MT_MB Exclusive_Unblock [1712017 ] 1712017
MT_MB MEM_Inv [0 ] 0
M_MB L1_GET_INSTR [0 ] 0
MT_IIB L1_GETS [0 ] 0
MT_IIB L1_GETX [0 ] 0
MT_IIB L1_UPGRADE [0 ] 0
-MT_IIB L1_PUTX [0 ] 0
+MT_IIB L1_PUTX [3 ] 3
MT_IIB L1_PUTX_old [0 ] 0
MT_IIB L2_Replacement [0 ] 0
MT_IIB L2_Replacement_clean [0 ] 0
-MT_IIB WB_Data [43373 ] 43373
-MT_IIB WB_Data_clean [622 ] 622
-MT_IIB Unblock [42 ] 42
+MT_IIB WB_Data [23620 ] 23620
+MT_IIB WB_Data_clean [502 ] 502
+MT_IIB Unblock [11 ] 11
MT_IIB MEM_Inv [0 ] 0
MT_IB L1_GET_INSTR [0 ] 0
MT_IB L1_PUTX_old [0 ] 0
MT_IB L2_Replacement [0 ] 0
MT_IB L2_Replacement_clean [0 ] 0
-MT_IB WB_Data [42 ] 42
+MT_IB WB_Data [11 ] 11
MT_IB WB_Data_clean [0 ] 0
MT_IB Unblock_Cancel [0 ] 0
MT_IB MEM_Inv [0 ] 0
MT_SB L1_PUTX_old [0 ] 0
MT_SB L2_Replacement [0 ] 0
MT_SB L2_Replacement_clean [0 ] 0
-MT_SB Unblock [43995 ] 43995
+MT_SB Unblock [24122 ] 24122
MT_SB MEM_Inv [0 ] 0
Memory controller: system.ruby.dir_cntrl0.memBuffer:
- memory_total_requests: 266571
- memory_reads: 172147
- memory_writes: 94424
- memory_refreshes: 536635
- memory_total_request_delays: 1016542
- memory_delays_per_request: 3.8134
- memory_delays_in_input_queue: 40049
- memory_delays_behind_head_of_bank_queue: 7609
- memory_delays_stalled_at_head_of_bank_queue: 968884
- memory_stalls_for_bank_busy: 959552
+ memory_total_requests: 274163
+ memory_reads: 177640
+ memory_writes: 96523
+ memory_refreshes: 588410
+ memory_total_request_delays: 1038324
+ memory_delays_per_request: 3.78725
+ memory_delays_in_input_queue: 39505
+ memory_delays_behind_head_of_bank_queue: 7889
+ memory_delays_stalled_at_head_of_bank_queue: 990930
+ memory_stalls_for_bank_busy: 981321
memory_stalls_for_random_busy: 0
memory_stalls_for_anti_starvation: 0
- memory_stalls_for_arbitration: 2148
- memory_stalls_for_bus: 7162
+ memory_stalls_for_arbitration: 2239
+ memory_stalls_for_bus: 7329
memory_stalls_for_tfaw: 0
- memory_stalls_for_read_write_turnaround: 15
- memory_stalls_for_read_read_turnaround: 7
- accesses_per_bank: 8989 7974 8010 8055 8487 8273 8235 8188 8380 8237 8148 8446 8268 8048 8068 7184 8265 8304 8191 8114 8382 8281 8178 8162 8416 8296 8511 9107 9086 9056 8973 8259
+ memory_stalls_for_read_write_turnaround: 29
+ memory_stalls_for_read_read_turnaround: 12
+ accesses_per_bank: 9082 9112 8244 8400 9230 8573 8966 8230 8398 8230 8230 8246 8347 8114 8111 7298 8351 8467 8382 8429 8595 8485 8298 8250 8587 8384 8675 9378 9287 9169 10231 8384
--- Directory ---
- Event Counts -
-Fetch [172147 ] 172147
-Data [94424 ] 94424
-Memory_Data [172147 ] 172147
-Memory_Ack [94424 ] 94424
+Fetch [177640 ] 177640
+Data [96523 ] 96523
+Memory_Data [177640 ] 177640
+Memory_Ack [96523 ] 96523
DMA_READ [0 ] 0
DMA_WRITE [0 ] 0
-CleanReplacement [12193 ] 12193
+CleanReplacement [15587 ] 15587
- Transitions -
-I Fetch [172147 ] 172147
+I Fetch [177640 ] 177640
I DMA_READ [0 ] 0
I DMA_WRITE [0 ] 0
ID_W DMA_READ [0 ] 0
ID_W DMA_WRITE [0 ] 0
-M Data [94424 ] 94424
+M Data [96523 ] 96523
M DMA_READ [0 ] 0
M DMA_WRITE [0 ] 0
-M CleanReplacement [12193 ] 12193
+M CleanReplacement [15587 ] 15587
IM Fetch [0 ] 0
IM Data [0 ] 0
-IM Memory_Data [172147 ] 172147
+IM Memory_Data [177640 ] 177640
IM DMA_READ [0 ] 0
IM DMA_WRITE [0 ] 0
MI Fetch [0 ] 0
MI Data [0 ] 0
-MI Memory_Ack [94424 ] 94424
+MI Memory_Ack [96523 ] 96523
MI DMA_READ [0 ] 0
MI DMA_WRITE [0 ] 0
+warn: add_child('terminal'): child 'terminal' already has parent
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Oct 27 2012 15:33:48
-gem5 started Oct 27 2012 15:33:58
+gem5 compiled Mar 28 2013 10:05:24
+gem5 started Mar 28 2013 10:05:51
gem5 executing on ribera.cs.wisc.edu
command line: build/X86_MESI_CMP_directory/gem5.opt -d build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/X86_MESI_CMP_directory/tests/opt/long/fs/10.linux-boot/x86/linux/pc-simple-timing-ruby-MESI_CMP_directory
-warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9.smp
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5205006494000 because m5_exit instruction encountered
+Exiting @ tick 5208135619000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.204983 # Number of seconds simulated
-sim_ticks 5204982530500 # Number of ticks simulated
-final_tick 5204982530500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.208136 # Number of seconds simulated
+sim_ticks 5208135619000 # Number of ticks simulated
+final_tick 5208135619000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 97445 # Simulator instruction rate (inst/s)
-host_op_rate 186950 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 4697195864 # Simulator tick rate (ticks/s)
-host_mem_usage 811856 # Number of bytes of host memory used
-host_seconds 1108.10 # Real time elapsed on the host
-sim_insts 107979048 # Number of instructions simulated
-sim_ops 207160548 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 35152 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.dtb.walker 137616 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.itb.walker 65352 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.inst 864449144 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu0.data 69078721 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.dtb.walker 87568 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.itb.walker 42392 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.inst 160961656 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu1.data 27339822 # Number of bytes read from this memory
-system.physmem.bytes_read::total 1122197423 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu0.inst 864449144 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::cpu1.inst 160961656 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 1025410800 # Number of instructions bytes read from this memory
+host_inst_rate 129465 # Simulator instruction rate (inst/s)
+host_op_rate 248187 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 6321029655 # Simulator tick rate (ticks/s)
+host_mem_usage 868876 # Number of bytes of host memory used
+host_seconds 823.94 # Real time elapsed on the host
+sim_insts 106670761 # Number of instructions simulated
+sim_ops 204490715 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 35248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.dtb.walker 110464 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.itb.walker 48224 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.inst 539219248 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu0.data 38302123 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.dtb.walker 112752 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.itb.walker 59160 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.inst 471821984 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu1.data 55029081 # Number of bytes read from this memory
+system.physmem.bytes_read::total 1104738284 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu0.inst 539219248 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::cpu1.inst 471821984 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 1011041232 # Number of instructions bytes read from this memory
system.physmem.bytes_written::pc.south_bridge.ide 2991104 # Number of bytes written to this memory
system.physmem.bytes_written::cpu0.itb.walker 16 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu0.data 48342743 # Number of bytes written to this memory
-system.physmem.bytes_written::cpu1.data 21309908 # Number of bytes written to this memory
-system.physmem.bytes_written::total 72643771 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 810 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.dtb.walker 17202 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.itb.walker 8169 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.inst 108056143 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu0.data 12053062 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.dtb.walker 10946 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.itb.walker 5299 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.inst 20120207 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu1.data 4057616 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 144329454 # Number of read requests responded to by this memory
+system.physmem.bytes_written::cpu0.data 30881325 # Number of bytes written to this memory
+system.physmem.bytes_written::cpu1.data 36960563 # Number of bytes written to this memory
+system.physmem.bytes_written::total 70833008 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 822 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.dtb.walker 13808 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.itb.walker 6028 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.inst 67402406 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu0.data 6418181 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.dtb.walker 14094 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.itb.walker 7395 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.inst 58977748 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu1.data 9244544 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 142085026 # Number of read requests responded to by this memory
system.physmem.num_writes::pc.south_bridge.ide 46736 # Number of write requests responded to by this memory
system.physmem.num_writes::cpu0.itb.walker 2 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu0.data 7125507 # Number of write requests responded to by this memory
-system.physmem.num_writes::cpu1.data 2934464 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 10106709 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 6754 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.dtb.walker 26439 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.itb.walker 12556 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.inst 166081085 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu0.data 13271653 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.dtb.walker 16824 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.itb.walker 8145 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.inst 30924533 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu1.data 5252625 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 215600613 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu0.inst 166081085 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu1.inst 30924533 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 197005618 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::pc.south_bridge.ide 574662 # Write bandwidth from this memory (bytes/s)
+system.physmem.num_writes::cpu0.data 4645692 # Number of write requests responded to by this memory
+system.physmem.num_writes::cpu1.data 5165176 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 9857606 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 6768 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.dtb.walker 21210 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.itb.walker 9259 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.inst 103534026 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu0.data 7354287 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.dtb.walker 21649 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.itb.walker 11359 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.inst 90593260 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu1.data 10565985 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 212117803 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu0.inst 103534026 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu1.inst 90593260 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 194127286 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::pc.south_bridge.ide 574314 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::cpu0.itb.walker 3 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu0.data 9287782 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::cpu1.data 4094136 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 13956583 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 581415 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.dtb.walker 26439 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.itb.walker 12559 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.inst 166081085 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu0.data 22559435 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.dtb.walker 16824 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.itb.walker 8145 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.inst 30924533 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu1.data 9346761 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 229557196 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 810 # Total number of read requests seen
+system.physmem.bw_write::cpu0.data 5929439 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::cpu1.data 7096697 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 13600454 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 581082 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.dtb.walker 21210 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.itb.walker 9262 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.inst 103534026 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu0.data 13283726 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.dtb.walker 21649 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.itb.walker 11359 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.inst 90593260 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu1.data 17662682 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 225718257 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 822 # Total number of read requests seen
system.physmem.writeReqs 46736 # Total number of write requests seen
system.physmem.cpureqs 47278 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 51840 # Total number of bytes read from memory
+system.physmem.bytesRead 52608 # Total number of bytes read from memory
system.physmem.bytesWritten 2991104 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 35152 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedRd 35248 # bytesRead derated as per pkt->getSize()
system.physmem.bytesConsumedWr 2991104 # bytesWritten derated as per pkt->getSize()
system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 298 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 16 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 48 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 96 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::0 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 64 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 326 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 16 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 48 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 32 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 48 # Track reads on a per bank basis
system.physmem.perBankRdReqs::11 16 # Track reads on a per bank basis
system.physmem.perBankRdReqs::12 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::13 32 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 96 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 0 # Track reads on a per bank basis
system.physmem.perBankRdReqs::15 48 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 2952 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 2848 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 3008 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 2928 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 2928 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 2944 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 3056 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 2944 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 2848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::0 2992 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 2928 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 2960 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 2784 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 2944 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 2848 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 2856 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 2912 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 2952 # Track writes on a per bank basis
system.physmem.perBankWrReqs::9 2912 # Track writes on a per bank basis
system.physmem.perBankWrReqs::10 2848 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 2704 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 2864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 2864 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 3048 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 3040 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 2832 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 3024 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 2992 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 2976 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 2976 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
system.physmem.numWrRetry 30 # Number of times wr buffer was full causing retry
-system.physmem.totGap 63182142000 # Total gap between requests
+system.physmem.totGap 67214585000 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
-system.physmem.readPktSize::3 298 # Categorize read packet sizes
+system.physmem.readPktSize::3 310 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
system.physmem.readPktSize::6 512 # Categorize read packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
system.physmem.writePktSize::6 46736 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 328 # What read queue length does an incoming req see
+system.physmem.rdQLenPdf::0 340 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 30 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 2 # What read queue length does an incoming req see
-system.physmem.wrQLenPdf::0 1965 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::1 1971 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::0 1967 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::1 1977 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1995 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1995 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::5 1996 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::6 1996 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::7 1999 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::8 1999 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::5 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::6 1995 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::7 1996 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::8 2000 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 2032 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 2032 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::23 67 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::24 61 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::23 65 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::24 55 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 37 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 37 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::28 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::29 36 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::30 33 # What write queue length does an incoming req see
-system.physmem.wrQLenPdf::31 33 # What write queue length does an incoming req see
-system.physmem.totQLat 40945522 # Total cycles spent in queuing delays
-system.physmem.totMemAccLat 52544272 # Sum of mem lat for all requests
-system.physmem.totBusLat 4050000 # Total cycles spent in databus access
-system.physmem.totBankLat 7548750 # Total cycles spent in bank access
-system.physmem.avgQLat 50550.03 # Average queueing delay per request
-system.physmem.avgBankLat 9319.44 # Average bank access latency per request
+system.physmem.wrQLenPdf::28 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::29 37 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::30 36 # What write queue length does an incoming req see
+system.physmem.wrQLenPdf::31 32 # What write queue length does an incoming req see
+system.physmem.totQLat 44820022 # Total cycles spent in queuing delays
+system.physmem.totMemAccLat 56685022 # Sum of mem lat for all requests
+system.physmem.totBusLat 4110000 # Total cycles spent in databus access
+system.physmem.totBankLat 7755000 # Total cycles spent in bank access
+system.physmem.avgQLat 54525.57 # Average queueing delay per request
+system.physmem.avgBankLat 9434.31 # Average bank access latency per request
system.physmem.avgBusLat 5000.00 # Average bus latency per request
-system.physmem.avgMemAccLat 64869.47 # Average memory access latency
+system.physmem.avgMemAccLat 68959.88 # Average memory access latency
system.physmem.avgRdBW 0.01 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 0.57 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 0.01 # Average consumed read bandwidth in MB/s
system.physmem.busUtil 0.00 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
system.physmem.avgWrQLen 0.15 # Average write queue length over time
-system.physmem.readRowHits 696 # Number of row buffer hits during reads
-system.physmem.writeRowHits 45224 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 85.93 # Row buffer hit rate for reads
+system.physmem.readRowHits 707 # Number of row buffer hits during reads
+system.physmem.writeRowHits 45223 # Number of row buffer hits during writes
+system.physmem.readRowHitRate 86.01 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 96.76 # Row buffer hit rate for writes
-system.physmem.avgGap 1328863.46 # Average gap between requests
+system.physmem.avgGap 1413318.16 # Average gap between requests
system.pc.south_bridge.ide.disks0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_bytes 32768 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks0.dma_read_txs 30 # Number of DMA read transactions (not PRD).
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_writes 0 # number of tag array writes
system.ruby.l2_cntrl0.L2cacheMemory.num_tag_array_stalls 0 # number of stalls caused by tag array
system.ruby.l2_cntrl0.L2cacheMemory.num_data_array_stalls 0 # number of stalls caused by data array
-system.cpu0.numCycles 10407785676 # number of cpu cycles simulated
+system.cpu0.numCycles 10415384713 # number of cpu cycles simulated
system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu0.committedInsts 92551738 # Number of instructions committed
-system.cpu0.committedOps 178518541 # Number of ops (including micro ops) committed
-system.cpu0.num_int_alu_accesses 168457745 # Number of integer alu accesses
+system.cpu0.committedInsts 58007070 # Number of instructions committed
+system.cpu0.committedOps 111693294 # Number of ops (including micro ops) committed
+system.cpu0.num_int_alu_accesses 104699305 # Number of integer alu accesses
system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu0.num_func_calls 0 # number of times a function call or return occured
-system.cpu0.num_conditional_control_insts 16414009 # number of instructions that are conditional controls
-system.cpu0.num_int_insts 168457745 # number of integer instructions
+system.cpu0.num_conditional_control_insts 9926831 # number of instructions that are conditional controls
+system.cpu0.num_int_insts 104699305 # number of integer instructions
system.cpu0.num_fp_insts 0 # number of float instructions
-system.cpu0.num_int_register_reads 415888462 # number of times the integer registers were read
-system.cpu0.num_int_register_writes 210334505 # number of times the integer registers were written
+system.cpu0.num_int_register_reads 256785271 # number of times the integer registers were read
+system.cpu0.num_int_register_writes 132412981 # number of times the integer registers were written
system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu0.num_mem_refs 20039556 # number of memory refs
-system.cpu0.num_load_insts 12899829 # Number of load instructions
-system.cpu0.num_store_insts 7139727 # Number of store instructions
-system.cpu0.num_idle_cycles 9669887390.939814 # Number of idle cycles
-system.cpu0.num_busy_cycles 737898285.060187 # Number of busy cycles
-system.cpu0.not_idle_fraction 0.070899 # Percentage of non-idle cycles
-system.cpu0.idle_fraction 0.929101 # Percentage of idle cycles
+system.cpu0.num_mem_refs 11918647 # number of memory refs
+system.cpu0.num_load_insts 7262283 # Number of load instructions
+system.cpu0.num_store_insts 4656364 # Number of store instructions
+system.cpu0.num_idle_cycles 9902585340.160280 # Number of idle cycles
+system.cpu0.num_busy_cycles 512799372.839719 # Number of busy cycles
+system.cpu0.not_idle_fraction 0.049235 # Percentage of non-idle cycles
+system.cpu0.idle_fraction 0.950765 # Percentage of idle cycles
system.cpu0.kern.inst.arm 0 # number of arm instructions executed
system.cpu0.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu1.numCycles 10409965061 # number of cpu cycles simulated
+system.cpu1.numCycles 10416271238 # number of cpu cycles simulated
system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu1.committedInsts 15427310 # Number of instructions committed
-system.cpu1.committedOps 28642007 # Number of ops (including micro ops) committed
-system.cpu1.num_int_alu_accesses 28123684 # Number of integer alu accesses
+system.cpu1.committedInsts 48663691 # Number of instructions committed
+system.cpu1.committedOps 92797421 # Number of ops (including micro ops) committed
+system.cpu1.num_int_alu_accesses 89245391 # Number of integer alu accesses
system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu1.num_func_calls 0 # number of times a function call or return occured
-system.cpu1.num_conditional_control_insts 1978311 # number of instructions that are conditional controls
-system.cpu1.num_int_insts 28123684 # number of integer instructions
+system.cpu1.num_conditional_control_insts 8303775 # number of instructions that are conditional controls
+system.cpu1.num_int_insts 89245391 # number of integer instructions
system.cpu1.num_fp_insts 0 # number of float instructions
-system.cpu1.num_int_register_reads 73029212 # number of times the integer registers were read
-system.cpu1.num_int_register_writes 31865924 # number of times the integer registers were written
+system.cpu1.num_int_register_reads 224679883 # number of times the integer registers were read
+system.cpu1.num_int_register_writes 106822538 # number of times the integer registers were written
system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu1.num_mem_refs 7025200 # number of memory refs
-system.cpu1.num_load_insts 4066766 # Number of load instructions
-system.cpu1.num_store_insts 2958434 # Number of store instructions
-system.cpu1.num_idle_cycles 10280018132.934025 # Number of idle cycles
-system.cpu1.num_busy_cycles 129946928.065975 # Number of busy cycles
-system.cpu1.not_idle_fraction 0.012483 # Percentage of non-idle cycles
-system.cpu1.idle_fraction 0.987517 # Percentage of idle cycles
+system.cpu1.num_mem_refs 14447171 # number of memory refs
+system.cpu1.num_load_insts 9256256 # Number of load instructions
+system.cpu1.num_store_insts 5190915 # Number of store instructions
+system.cpu1.num_idle_cycles 10072379281.574066 # Number of idle cycles
+system.cpu1.num_busy_cycles 343891956.425934 # Number of busy cycles
+system.cpu1.not_idle_fraction 0.033015 # Percentage of non-idle cycles
+system.cpu1.idle_fraction 0.966985 # Percentage of idle cycles
system.cpu1.kern.inst.arm 0 # number of arm instructions executed
system.cpu1.kern.inst.quiesce 0 # number of quiesce instructions executed
[system.cpu.interrupts]
type=X86LocalApic
-clock=500
+clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
block_size=64
clock=500
header_cycles=1
+system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
[system.e820_table]
type=X86E820Table
-children=entries0 entries1
-entries=system.e820_table.entries0 system.e820_table.entries1
+children=entries0 entries1 entries2
+entries=system.e820_table.entries0 system.e820_table.entries1 system.e820_table.entries2
[system.e820_table.entries0]
type=X86E820Entry
addr=0
-range_type=2
-size=1048576
+range_type=1
+size=654336
[system.e820_table.entries1]
type=X86E820Entry
+addr=654336
+range_type=2
+size=394240
+
+[system.e820_table.entries2]
+type=X86E820Entry
addr=1048576
range_type=1
size=133169152
block_size=64
clock=1000
header_cycles=1
+system=system
use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
+activation_limit=4
addr_mapping=openmap
banks_per_rank=8
+channels=1
clock=1000
conf_table_reported=false
in_addr_map=true
-lines_per_rowbuffer=64
-mem_sched_policy=fcfs
+lines_per_rowbuffer=32
+mem_sched_policy=frfcfs
null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
+warn: add_child('terminal'): child 'terminal' already has parent
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 16:30:44
-gem5 started Jan 23 2013 18:32:27
+gem5 compiled Mar 28 2013 09:59:18
+gem5 started Mar 28 2013 09:59:40
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-atomic
-warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5112040970500 because m5_exit instruction encountered
+Exiting @ tick 5112099860500 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.112041 # Number of seconds simulated
-sim_ticks 5112040970500 # Number of ticks simulated
-final_tick 5112040970500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.112100 # Number of seconds simulated
+sim_ticks 5112099860500 # Number of ticks simulated
+final_tick 5112099860500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 1074050 # Simulator instruction rate (inst/s)
-host_op_rate 2199194 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 27479001055 # Simulator tick rate (ticks/s)
-host_mem_usage 583620 # Number of bytes of host memory used
-host_seconds 186.03 # Real time elapsed on the host
-sim_insts 199810242 # Number of instructions simulated
-sim_ops 409125913 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2464640 # Number of bytes read from this memory
+host_inst_rate 1028107 # Simulator instruction rate (inst/s)
+host_op_rate 2105009 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 26291327617 # Simulator tick rate (ticks/s)
+host_mem_usage 628192 # Number of bytes of host memory used
+host_seconds 194.44 # Real time elapsed on the host
+sim_insts 199905607 # Number of instructions simulated
+sim_ops 409299132 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2420928 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.dtb.walker 128 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 853824 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 10600128 # Number of bytes read from this memory
-system.physmem.bytes_read::total 13919040 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 853824 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 853824 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 9292608 # Number of bytes written to this memory
-system.physmem.bytes_written::total 9292608 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 38510 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 852736 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 10605184 # Number of bytes read from this memory
+system.physmem.bytes_read::total 13879296 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 852736 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 852736 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 9264448 # Number of bytes written to this memory
+system.physmem.bytes_written::total 9264448 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 37827 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.dtb.walker 2 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 13341 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 165627 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 217485 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 145197 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 145197 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 482124 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 13324 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 165706 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 216864 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 144757 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 144757 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 473568 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.dtb.walker 25 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 63 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 167022 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 2073561 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2722795 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 167022 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 167022 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1817788 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1817788 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1817788 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 482124 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 166807 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 2074526 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2714989 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 166807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 166807 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1812259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1812259 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1812259 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 473568 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.dtb.walker 25 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 63 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 167022 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 2073561 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4540583 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.inst 166807 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 2074526 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4527248 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 0 # Total number of read requests seen
system.physmem.writeReqs 0 # Total number of write requests seen
system.physmem.cpureqs 0 # Reqs generatd by CPU via cache - shady
system.physmem.readRowHitRate nan # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap nan # Average gap between requests
-system.iocache.replacements 47569 # number of replacements
-system.iocache.tagsinuse 0.042402 # Cycle average of tags in use
+system.iocache.replacements 47568 # number of replacements
+system.iocache.tagsinuse 0.042441 # Cycle average of tags in use
system.iocache.total_refs 0 # Total number of references to valid blocks.
-system.iocache.sampled_refs 47585 # Sample count of references to valid blocks.
+system.iocache.sampled_refs 47584 # Sample count of references to valid blocks.
system.iocache.avg_refs 0 # Average number of references to valid blocks.
-system.iocache.warmup_cycle 4994776682059 # Cycle when the warmup percentage was hit.
-system.iocache.occ_blocks::pc.south_bridge.ide 0.042402 # Average occupied blocks per requestor
-system.iocache.occ_percent::pc.south_bridge.ide 0.002650 # Average percentage of cache occupancy
-system.iocache.occ_percent::total 0.002650 # Average percentage of cache occupancy
-system.iocache.ReadReq_misses::pc.south_bridge.ide 904 # number of ReadReq misses
-system.iocache.ReadReq_misses::total 904 # number of ReadReq misses
+system.iocache.warmup_cycle 4994822603059 # Cycle when the warmup percentage was hit.
+system.iocache.occ_blocks::pc.south_bridge.ide 0.042441 # Average occupied blocks per requestor
+system.iocache.occ_percent::pc.south_bridge.ide 0.002653 # Average percentage of cache occupancy
+system.iocache.occ_percent::total 0.002653 # Average percentage of cache occupancy
+system.iocache.ReadReq_misses::pc.south_bridge.ide 903 # number of ReadReq misses
+system.iocache.ReadReq_misses::total 903 # number of ReadReq misses
system.iocache.WriteReq_misses::pc.south_bridge.ide 46720 # number of WriteReq misses
system.iocache.WriteReq_misses::total 46720 # number of WriteReq misses
-system.iocache.demand_misses::pc.south_bridge.ide 47624 # number of demand (read+write) misses
-system.iocache.demand_misses::total 47624 # number of demand (read+write) misses
-system.iocache.overall_misses::pc.south_bridge.ide 47624 # number of overall misses
-system.iocache.overall_misses::total 47624 # number of overall misses
-system.iocache.ReadReq_accesses::pc.south_bridge.ide 904 # number of ReadReq accesses(hits+misses)
-system.iocache.ReadReq_accesses::total 904 # number of ReadReq accesses(hits+misses)
+system.iocache.demand_misses::pc.south_bridge.ide 47623 # number of demand (read+write) misses
+system.iocache.demand_misses::total 47623 # number of demand (read+write) misses
+system.iocache.overall_misses::pc.south_bridge.ide 47623 # number of overall misses
+system.iocache.overall_misses::total 47623 # number of overall misses
+system.iocache.ReadReq_accesses::pc.south_bridge.ide 903 # number of ReadReq accesses(hits+misses)
+system.iocache.ReadReq_accesses::total 903 # number of ReadReq accesses(hits+misses)
system.iocache.WriteReq_accesses::pc.south_bridge.ide 46720 # number of WriteReq accesses(hits+misses)
system.iocache.WriteReq_accesses::total 46720 # number of WriteReq accesses(hits+misses)
-system.iocache.demand_accesses::pc.south_bridge.ide 47624 # number of demand (read+write) accesses
-system.iocache.demand_accesses::total 47624 # number of demand (read+write) accesses
-system.iocache.overall_accesses::pc.south_bridge.ide 47624 # number of overall (read+write) accesses
-system.iocache.overall_accesses::total 47624 # number of overall (read+write) accesses
+system.iocache.demand_accesses::pc.south_bridge.ide 47623 # number of demand (read+write) accesses
+system.iocache.demand_accesses::total 47623 # number of demand (read+write) accesses
+system.iocache.overall_accesses::pc.south_bridge.ide 47623 # number of overall (read+write) accesses
+system.iocache.overall_accesses::total 47623 # number of overall (read+write) accesses
system.iocache.ReadReq_miss_rate::pc.south_bridge.ide 1 # miss rate for ReadReq accesses
system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
system.iocache.WriteReq_miss_rate::pc.south_bridge.ide 1 # miss rate for WriteReq accesses
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
-system.cpu.numCycles 10224081964 # number of cpu cycles simulated
+system.cpu.numCycles 10224199744 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
-system.cpu.committedInsts 199810242 # Number of instructions committed
-system.cpu.committedOps 409125913 # Number of ops (including micro ops) committed
-system.cpu.num_int_alu_accesses 374289904 # Number of integer alu accesses
+system.cpu.committedInsts 199905607 # Number of instructions committed
+system.cpu.committedOps 409299132 # Number of ops (including micro ops) committed
+system.cpu.num_int_alu_accesses 374462045 # Number of integer alu accesses
system.cpu.num_fp_alu_accesses 0 # Number of float alu accesses
system.cpu.num_func_calls 0 # number of times a function call or return occured
-system.cpu.num_conditional_control_insts 39954533 # number of instructions that are conditional controls
-system.cpu.num_int_insts 374289904 # number of integer instructions
+system.cpu.num_conditional_control_insts 39972114 # number of instructions that are conditional controls
+system.cpu.num_int_insts 374462045 # number of integer instructions
system.cpu.num_fp_insts 0 # number of float instructions
-system.cpu.num_int_register_reads 915450656 # number of times the integer registers were read
-system.cpu.num_int_register_writes 480322719 # number of times the integer registers were written
+system.cpu.num_int_register_reads 915890298 # number of times the integer registers were read
+system.cpu.num_int_register_writes 480542887 # number of times the integer registers were written
system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
-system.cpu.num_mem_refs 35624590 # number of memory refs
-system.cpu.num_load_insts 27216588 # Number of load instructions
-system.cpu.num_store_insts 8408002 # Number of store instructions
-system.cpu.num_idle_cycles 9770609609.165962 # Number of idle cycles
-system.cpu.num_busy_cycles 453472354.834038 # Number of busy cycles
-system.cpu.not_idle_fraction 0.044353 # Percentage of non-idle cycles
-system.cpu.idle_fraction 0.955647 # Percentage of idle cycles
+system.cpu.num_mem_refs 35654170 # number of memory refs
+system.cpu.num_load_insts 27234345 # Number of load instructions
+system.cpu.num_store_insts 8419825 # Number of store instructions
+system.cpu.num_idle_cycles 9770518400.401503 # Number of idle cycles
+system.cpu.num_busy_cycles 453681343.598497 # Number of busy cycles
+system.cpu.not_idle_fraction 0.044373 # Percentage of non-idle cycles
+system.cpu.idle_fraction 0.955627 # Percentage of idle cycles
system.cpu.kern.inst.arm 0 # number of arm instructions executed
system.cpu.kern.inst.quiesce 0 # number of quiesce instructions executed
-system.cpu.icache.replacements 790732 # number of replacements
-system.cpu.icache.tagsinuse 510.627675 # Cycle average of tags in use
-system.cpu.icache.total_refs 243360727 # Total number of references to valid blocks.
-system.cpu.icache.sampled_refs 791244 # Sample count of references to valid blocks.
-system.cpu.icache.avg_refs 307.567232 # Average number of references to valid blocks.
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system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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-system.cpu.l2cache.tagsinuse 64822.149220 # Cycle average of tags in use
-system.cpu.l2cache.total_refs 3456224 # Total number of references to valid blocks.
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system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------
[system.cpu.interrupts]
type=X86LocalApic
-clock=500
+clock=8000
int_latency=1000
pio_addr=2305843009213693952
pio_latency=100000
block_size=64
clock=500
header_cycles=1
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use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
[system.e820_table]
type=X86E820Table
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+children=entries0 entries1 entries2
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[system.e820_table.entries0]
type=X86E820Entry
addr=0
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[system.e820_table.entries1]
type=X86E820Entry
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+
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addr=1048576
range_type=1
size=133169152
block_size=64
clock=1000
header_cycles=1
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use_default_range=false
width=8
default=system.membus.badaddr_responder.pio
[system.physmem]
type=SimpleDRAM
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addr_mapping=openmap
banks_per_rank=8
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clock=1000
conf_table_reported=false
in_addr_map=true
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null=false
page_policy=open
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
-tBURST=4000
-tCL=14000
-tRCD=14000
+tBURST=5000
+tCL=13750
+tRCD=13750
tREFI=7800000
tRFC=300000
-tRP=14000
-tWTR=1000
+tRP=13750
+tWTR=7500
+tXAW=40000
write_buffer_size=32
write_thresh_perc=70
zero=false
+warn: add_child('terminal'): child 'terminal' already has parent
warn: Sockets disabled, not accepting terminal connections
warn: Reading current count from inactive timer.
warn: Sockets disabled, not accepting gdb connections
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
-gem5 compiled Jan 23 2013 16:30:44
-gem5 started Jan 23 2013 18:02:27
+gem5 compiled Mar 28 2013 09:59:18
+gem5 started Mar 28 2013 09:59:40
gem5 executing on ribera.cs.wisc.edu
command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing -re tests/run.py build/X86/tests/opt/quick/fs/10.linux-boot/x86/linux/pc-simple-timing
-warning: add_child('terminal'): child 'terminal' already has parent
Global frequency set at 1000000000000 ticks per second
info: kernel located at: /scratch/nilay/GEM5/system/binaries/x86_64-vmlinux-2.6.22.9
0: rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 5191112864000 because m5_exit instruction encountered
+Exiting @ tick 5191816279000 because m5_exit instruction encountered
---------- Begin Simulation Statistics ----------
-sim_seconds 5.195162 # Number of seconds simulated
-sim_ticks 5195162021000 # Number of ticks simulated
-final_tick 5195162021000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
+sim_seconds 5.191816 # Number of seconds simulated
+sim_ticks 5191816279000 # Number of ticks simulated
+final_tick 5191816279000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
-host_inst_rate 434432 # Simulator instruction rate (inst/s)
-host_op_rate 837466 # Simulator op (including micro ops) rate (op/s)
-host_tick_rate 17594801878 # Simulator tick rate (ticks/s)
-host_mem_usage 611684 # Number of bytes of host memory used
-host_seconds 295.27 # Real time elapsed on the host
-sim_insts 128273373 # Number of instructions simulated
-sim_ops 247275988 # Number of ops (including micro ops) simulated
-system.physmem.bytes_read::pc.south_bridge.ide 2861312 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.dtb.walker 64 # Number of bytes read from this memory
+host_inst_rate 631596 # Simulator instruction rate (inst/s)
+host_op_rate 1217489 # Simulator op (including micro ops) rate (op/s)
+host_tick_rate 25553396248 # Simulator tick rate (ticks/s)
+host_mem_usage 629228 # Number of bytes of host memory used
+host_seconds 203.18 # Real time elapsed on the host
+sim_insts 128324646 # Number of instructions simulated
+sim_ops 247363464 # Number of ops (including micro ops) simulated
+system.physmem.bytes_read::pc.south_bridge.ide 2859648 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.itb.walker 320 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.inst 823744 # Number of bytes read from this memory
-system.physmem.bytes_read::cpu.data 9012160 # Number of bytes read from this memory
-system.physmem.bytes_read::total 12697600 # Number of bytes read from this memory
-system.physmem.bytes_inst_read::cpu.inst 823744 # Number of instructions bytes read from this memory
-system.physmem.bytes_inst_read::total 823744 # Number of instructions bytes read from this memory
-system.physmem.bytes_written::writebacks 8123136 # Number of bytes written to this memory
-system.physmem.bytes_written::total 8123136 # Number of bytes written to this memory
-system.physmem.num_reads::pc.south_bridge.ide 44708 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.dtb.walker 1 # Number of read requests responded to by this memory
+system.physmem.bytes_read::cpu.inst 823360 # Number of bytes read from this memory
+system.physmem.bytes_read::cpu.data 9009408 # Number of bytes read from this memory
+system.physmem.bytes_read::total 12692736 # Number of bytes read from this memory
+system.physmem.bytes_inst_read::cpu.inst 823360 # Number of instructions bytes read from this memory
+system.physmem.bytes_inst_read::total 823360 # Number of instructions bytes read from this memory
+system.physmem.bytes_written::writebacks 8106432 # Number of bytes written to this memory
+system.physmem.bytes_written::total 8106432 # Number of bytes written to this memory
+system.physmem.num_reads::pc.south_bridge.ide 44682 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.itb.walker 5 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.inst 12871 # Number of read requests responded to by this memory
-system.physmem.num_reads::cpu.data 140815 # Number of read requests responded to by this memory
-system.physmem.num_reads::total 198400 # Number of read requests responded to by this memory
-system.physmem.num_writes::writebacks 126924 # Number of write requests responded to by this memory
-system.physmem.num_writes::total 126924 # Number of write requests responded to by this memory
-system.physmem.bw_read::pc.south_bridge.ide 550765 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.dtb.walker 12 # Total read bandwidth from this memory (bytes/s)
+system.physmem.num_reads::cpu.inst 12865 # Number of read requests responded to by this memory
+system.physmem.num_reads::cpu.data 140772 # Number of read requests responded to by this memory
+system.physmem.num_reads::total 198324 # Number of read requests responded to by this memory
+system.physmem.num_writes::writebacks 126663 # Number of write requests responded to by this memory
+system.physmem.num_writes::total 126663 # Number of write requests responded to by this memory
+system.physmem.bw_read::pc.south_bridge.ide 550799 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.itb.walker 62 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.inst 158560 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::cpu.data 1734722 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_read::total 2444120 # Total read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::cpu.inst 158560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_inst_read::total 158560 # Instruction read bandwidth from this memory (bytes/s)
-system.physmem.bw_write::writebacks 1563596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_write::total 1563596 # Write bandwidth from this memory (bytes/s)
-system.physmem.bw_total::writebacks 1563596 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::pc.south_bridge.ide 550765 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.dtb.walker 12 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_read::cpu.inst 158588 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::cpu.data 1735309 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_read::total 2444758 # Total read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::cpu.inst 158588 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_inst_read::total 158588 # Instruction read bandwidth from this memory (bytes/s)
+system.physmem.bw_write::writebacks 1561387 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_write::total 1561387 # Write bandwidth from this memory (bytes/s)
+system.physmem.bw_total::writebacks 1561387 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::pc.south_bridge.ide 550799 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.itb.walker 62 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.inst 158560 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::cpu.data 1734722 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.bw_total::total 4007716 # Total bandwidth to/from this memory (bytes/s)
-system.physmem.readReqs 198400 # Total number of read requests seen
-system.physmem.writeReqs 126924 # Total number of write requests seen
-system.physmem.cpureqs 326952 # Reqs generatd by CPU via cache - shady
-system.physmem.bytesRead 12697600 # Total number of bytes read from memory
-system.physmem.bytesWritten 8123136 # Total number of bytes written to memory
-system.physmem.bytesConsumedRd 12697600 # bytesRead derated as per pkt->getSize()
-system.physmem.bytesConsumedWr 8123136 # bytesWritten derated as per pkt->getSize()
-system.physmem.servicedByWrQ 57 # Number of read reqs serviced by write Q
-system.physmem.neitherReadNorWrite 1624 # Reqs where no action is needed
-system.physmem.perBankRdReqs::0 12569 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::1 12080 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::2 12234 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::3 12524 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::4 12268 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::5 12127 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::6 12566 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::7 12719 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::8 12479 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::9 12349 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::10 12465 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::11 12500 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::12 12468 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::13 12050 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::14 12371 # Track reads on a per bank basis
-system.physmem.perBankRdReqs::15 12574 # Track reads on a per bank basis
-system.physmem.perBankWrReqs::0 8012 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::1 7683 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::2 7790 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::3 8089 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::4 7865 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::5 7679 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::6 8084 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::7 8243 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::8 8069 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::9 7980 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::10 7953 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::11 7969 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::12 7935 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::13 7628 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::14 7886 # Track writes on a per bank basis
-system.physmem.perBankWrReqs::15 8059 # Track writes on a per bank basis
+system.physmem.bw_total::cpu.inst 158588 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::cpu.data 1735309 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.bw_total::total 4006145 # Total bandwidth to/from this memory (bytes/s)
+system.physmem.readReqs 198324 # Total number of read requests seen
+system.physmem.writeReqs 126663 # Total number of write requests seen
+system.physmem.cpureqs 326610 # Reqs generatd by CPU via cache - shady
+system.physmem.bytesRead 12692736 # Total number of bytes read from memory
+system.physmem.bytesWritten 8106432 # Total number of bytes written to memory
+system.physmem.bytesConsumedRd 12692736 # bytesRead derated as per pkt->getSize()
+system.physmem.bytesConsumedWr 8106432 # bytesWritten derated as per pkt->getSize()
+system.physmem.servicedByWrQ 80 # Number of read reqs serviced by write Q
+system.physmem.neitherReadNorWrite 1618 # Reqs where no action is needed
+system.physmem.perBankRdReqs::0 12615 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::1 12250 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::2 12267 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::3 12575 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::4 12362 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::5 12187 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::6 12619 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::7 12562 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::8 12247 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::9 11965 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::10 12423 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::11 12610 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::12 12268 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::13 12172 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::14 12546 # Track reads on a per bank basis
+system.physmem.perBankRdReqs::15 12576 # Track reads on a per bank basis
+system.physmem.perBankWrReqs::0 8002 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::1 7779 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::2 7802 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::3 8120 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::4 7982 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::5 7804 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::6 8130 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::7 8156 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::8 7749 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::9 7475 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::10 7958 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::11 8068 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::12 7819 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::13 7741 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::14 7995 # Track writes on a per bank basis
+system.physmem.perBankWrReqs::15 8083 # Track writes on a per bank basis
system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
-system.physmem.numWrRetry 4 # Number of times wr buffer was full causing retry
-system.physmem.totGap 5195161957500 # Total gap between requests
+system.physmem.numWrRetry 5 # Number of times wr buffer was full causing retry
+system.physmem.totGap 5191816215500 # Total gap between requests
system.physmem.readPktSize::0 0 # Categorize read packet sizes
system.physmem.readPktSize::1 0 # Categorize read packet sizes
system.physmem.readPktSize::2 0 # Categorize read packet sizes
system.physmem.readPktSize::3 0 # Categorize read packet sizes
system.physmem.readPktSize::4 0 # Categorize read packet sizes
system.physmem.readPktSize::5 0 # Categorize read packet sizes
-system.physmem.readPktSize::6 198400 # Categorize read packet sizes
+system.physmem.readPktSize::6 198324 # Categorize read packet sizes
system.physmem.writePktSize::0 0 # Categorize write packet sizes
system.physmem.writePktSize::1 0 # Categorize write packet sizes
system.physmem.writePktSize::2 0 # Categorize write packet sizes
system.physmem.writePktSize::3 0 # Categorize write packet sizes
system.physmem.writePktSize::4 0 # Categorize write packet sizes
system.physmem.writePktSize::5 0 # Categorize write packet sizes
-system.physmem.writePktSize::6 126924 # Categorize write packet sizes
-system.physmem.rdQLenPdf::0 155109 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::1 8773 # What read queue length does an incoming req see
-system.physmem.rdQLenPdf::2 6640 # What read queue length does an incoming req see
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-system.physmem.rdQLenPdf::20 36 # What read queue length does an incoming req see
+system.physmem.writePktSize::6 126663 # Categorize write packet sizes
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system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
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system.physmem.wrQLenPdf::31 5 # What write queue length does an incoming req see
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-system.physmem.totMemAccLat 7915241249 # Sum of mem lat for all requests
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system.physmem.avgBusLat 5000.00 # Average bus latency per request
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system.physmem.avgRdBW 2.44 # Average achieved read bandwidth in MB/s
system.physmem.avgWrBW 1.56 # Average achieved write bandwidth in MB/s
system.physmem.avgConsumedRdBW 2.44 # Average consumed read bandwidth in MB/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.avgRdQLen 0.00 # Average read queue length over time
-system.physmem.avgWrQLen 12.66 # Average write queue length over time
-system.physmem.readRowHits 175593 # Number of row buffer hits during reads
-system.physmem.writeRowHits 94810 # Number of row buffer hits during writes
-system.physmem.readRowHitRate 88.53 # Row buffer hit rate for reads
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system.iocache.avg_refs 0 # Average number of references to valid blocks.
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system.iocache.ReadReq_miss_rate::total 1 # miss rate for ReadReq accesses
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system.iocache.blocked_cycles::no_targets 0 # number of cycles access was blocked
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system.iocache.blocked::no_targets 0 # number of cycles access was blocked
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system.iocache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.iocache.fast_writes 0 # number of fast writes performed
system.iocache.cache_copies 0 # number of cache copies performed
system.iocache.writebacks::writebacks 46667 # number of writebacks
system.iocache.writebacks::total 46667 # number of writebacks
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system.iocache.ReadReq_mshr_miss_rate::total 1 # mshr miss rate for ReadReq accesses
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system.iocache.no_allocate_misses 0 # Number of misses that were no-allocate
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system.pc.south_bridge.ide.disks0.dma_read_bytes 34816 # Number of bytes transfered via DMA reads (not PRD).
system.pc.south_bridge.ide.disks1.dma_write_full_pages 1 # Number of full page size DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_bytes 4096 # Number of bytes transfered via DMA writes.
system.pc.south_bridge.ide.disks1.dma_write_txs 1 # Number of DMA write transactions.
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system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
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system.cpu.num_fp_register_reads 0 # number of times the floating registers were read
system.cpu.num_fp_register_writes 0 # number of times the floating registers were written
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system.cpu.kern.inst.arm 0 # number of arm instructions executed
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.itb.walker 0.001629 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.016165 # mshr miss rate for ReadReq accesses
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+system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.019509 # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::cpu.data 0.808219 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.UpgradeReq_mshr_miss_rate::total 0.808219 # mshr miss rate for UpgradeReq accesses
+system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.361305 # mshr miss rate for ReadExReq accesses
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+system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.016165 # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.087468 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.itb.walker 56251 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49043.533017 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45712.487335 # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 46753.140004 # average ReadReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10716.162023 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10716.162023 # average UpgradeReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 36974.038224 # average ReadExReq mshr miss latency
-system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36974.038224 # average ReadExReq mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 49743.187859 # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 45358.380889 # average ReadReq mshr miss latency
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+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::cpu.data 10717.639646 # average UpgradeReq mshr miss latency
+system.cpu.l2cache.UpgradeReq_avg_mshr_miss_latency::total 10717.639646 # average UpgradeReq mshr miss latency
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+system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36952.748503 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.dtb.walker 56251 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49743.187859 # average overall mshr miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 38633.815660 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.itb.walker 56251 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49043.533017 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38723.972104 # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39583.742448 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49743.187859 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 38633.815660 # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39559.094455 # average overall mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::cpu.data inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.ReadReq_avg_mshr_uncacheable_latency::total inf # average ReadReq mshr uncacheable latency
system.cpu.l2cache.WriteReq_avg_mshr_uncacheable_latency::cpu.data inf # average WriteReq mshr uncacheable latency
projects / gem5.git / commitdiff