Tiny bugfix in simlib.v

diff --git a/techlibs/simlib.v b/techlibs/simlib.v
index 29c13503b5abeec336f70d48e84578656b215cf6..8675a4d0fceeafc1d31506f427034487095af5df 100644 (file)
--- a/techlibs/simlib.v
+++ b/techlibs/simlib.v
@@ -646,7 +646,6 @@ module \$sr (S, R, Q);
 
 parameter WIDTH = 0;
 
-input CLK;
 input [WIDTH-1:0] S, R;
 output reg [WIDTH-1:0] Q;