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perlbmk is a tru64 regression, not a linux one
authorGabe Black <gblack@eecs.umich.edu>
Sun, 11 Mar 2007 23:04:46 +0000 (19:04 -0400)
committerGabe Black <gblack@eecs.umich.edu>
Sun, 11 Mar 2007 23:04:46 +0000 (19:04 -0400)
--HG--
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
rename : tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout => tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
extra : convert_revision : 8241afcb6e79a7b85e6115bb829f8ef1345b3994

20 files changed:
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout [deleted file] patch | blob | history
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr [new file with mode: 0644] patch | blob
tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout [new file with mode: 0644] patch | blob

diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
deleted file mode 100644 (file)
index 59c6e25..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.ini
+++ /dev/null
@@ -1,90 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=AtomicSimpleCPU
-children=workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-simulate_stalls=false
-system=system
-width=1
-workload=system.cpu.workload
-dcache_port=system.membus.port[2]
-icache_port=system.membus.port[1]
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
deleted file mode 100644 (file)
index c6e4aa1..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/config.out
+++ /dev/null
@@ -1,80 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=AtomicSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-width=1
-function_trace=false
-function_trace_start=0
-simulate_stalls=false
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
deleted file mode 100644 (file)
index 9db3f64..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/m5stats.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate                                1149393                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 177516                       # Number of bytes of host memory used
-host_seconds                                  1747.87                       # Real time elapsed on the host
-host_tick_rate                                1149393                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  2008987607                       # Number of instructions simulated
-sim_seconds                                  0.002009                       # Number of seconds simulated
-sim_ticks                                  2008987606                       # Number of ticks simulated
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       2008987607                       # number of cpu cycles simulated
-system.cpu.num_insts                       2008987607                       # Number of instructions executed
-system.cpu.num_refs                         722390435                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
deleted file mode 100644 (file)
index bc72461..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stderr
+++ /dev/null
@@ -1,3 +0,0 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0.  Starting simulation...
-warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
deleted file mode 100644 (file)
index d4a078b..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-atomic/stdout
+++ /dev/null
@@ -1,1376 +0,0 @@
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diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
deleted file mode 100644 (file)
index 5f64dce..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.ini
+++ /dev/null
@@ -1,213 +0,0 @@
-[root]
-type=Root
-children=system
-checkpoint=
-clock=1000000000000
-max_tick=0
-output_file=cout
-progress_interval=0
-
-[serialize]
-count=10
-cycle=0
-dir=cpt.%012d
-period=0
-
-[stats]
-descriptions=true
-dump_cycle=0
-dump_period=0
-dump_reset=false
-ignore_events=
-mysql_db=
-mysql_host=
-mysql_password=
-mysql_user=
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_compat=true
-text_file=m5stats.txt
-
-[system]
-type=System
-children=cpu membus physmem
-mem_mode=atomic
-physmem=system.physmem
-
-[system.cpu]
-type=TimingSimpleCPU
-children=dcache icache l2cache toL2Bus workload
-clock=1
-cpu_id=0
-defer_registration=false
-function_trace=false
-function_trace_start=0
-max_insts_all_threads=0
-max_insts_any_thread=0
-max_loads_all_threads=0
-max_loads_any_thread=0
-phase=0
-progress_interval=0
-system=system
-workload=system.cpu.workload
-dcache_port=system.cpu.dcache.cpu_side
-icache_port=system.cpu.icache.cpu_side
-
-[system.cpu.dcache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=262144
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.dcache_port
-mem_side=system.cpu.toL2Bus.port[1]
-
-[system.cpu.icache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=131072
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.icache_port
-mem_side=system.cpu.toL2Bus.port[0]
-
-[system.cpu.l2cache]
-type=BaseCache
-adaptive_compression=false
-assoc=2
-block_size=64
-compressed_bus=false
-compression_latency=0
-hash_delay=1
-hit_latency=1
-latency=1
-lifo=false
-max_miss_count=0
-mshrs=10
-prefetch_access=false
-prefetch_cache_check_push=true
-prefetch_data_accesses_only=false
-prefetch_degree=1
-prefetch_latency=10
-prefetch_miss=false
-prefetch_past_page=false
-prefetch_policy=none
-prefetch_serial_squash=false
-prefetch_use_cpu_id=true
-prefetcher_size=100
-prioritizeRequests=false
-protocol=Null
-repl=Null
-size=2097152
-split=false
-split_size=0
-store_compressed=false
-subblock_size=0
-tgts_per_mshr=5
-trace_addr=0
-two_queue=false
-write_buffers=8
-cpu_side=system.cpu.toL2Bus.port[2]
-mem_side=system.membus.port[1]
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
-egid=100
-env=
-euid=100
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-gid=100
-input=cin
-output=cout
-pid=100
-ppid=99
-system=system
-uid=100
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-responder_set=false
-width=64
-port=system.physmem.port system.cpu.l2cache.mem_side
-
-[system.physmem]
-type=PhysicalMemory
-file=
-latency=1
-range=0:134217727
-zero=false
-port=system.membus.port[0]
-
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
deleted file mode 100644 (file)
index 6998f48..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/config.out
+++ /dev/null
@@ -1,201 +0,0 @@
-[root]
-type=Root
-clock=1000000000000
-max_tick=0
-progress_interval=0
-output_file=cout
-
-[system.physmem]
-type=PhysicalMemory
-file=
-range=[0,134217727]
-latency=1
-zero=false
-
-[system]
-type=System
-physmem=system.physmem
-mem_mode=atomic
-
-[system.membus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.workload]
-type=LiveProcess
-cmd=perlbmk -I. -I lib lgred.makerand.pl
-executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
-input=cin
-output=cout
-env=
-cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
-system=system
-uid=100
-euid=100
-gid=100
-egid=100
-pid=100
-ppid=99
-
-[system.cpu]
-type=TimingSimpleCPU
-max_insts_any_thread=0
-max_insts_all_threads=0
-max_loads_any_thread=0
-max_loads_all_threads=0
-progress_interval=0
-system=system
-cpu_id=0
-workload=system.cpu.workload
-clock=1
-phase=0
-defer_registration=false
-// width not specified
-function_trace=false
-function_trace_start=0
-// simulate_stalls not specified
-
-[system.cpu.toL2Bus]
-type=Bus
-bus_id=0
-clock=1000
-width=64
-responder_set=false
-
-[system.cpu.icache]
-type=BaseCache
-size=131072
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.dcache]
-type=BaseCache
-size=262144
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[system.cpu.l2cache]
-type=BaseCache
-size=2097152
-assoc=2
-block_size=64
-latency=1
-mshrs=10
-tgts_per_mshr=5
-write_buffers=8
-prioritizeRequests=false
-protocol=null
-trace_addr=0
-hash_delay=1
-repl=null
-compressed_bus=false
-store_compressed=false
-adaptive_compression=false
-compression_latency=0
-block_size=64
-max_miss_count=0
-addr_range=[0,18446744073709551615]
-split=false
-split_size=0
-lifo=false
-two_queue=false
-prefetch_miss=false
-prefetch_access=false
-prefetcher_size=100
-prefetch_past_page=false
-prefetch_serial_squash=false
-prefetch_latency=10
-prefetch_degree=1
-prefetch_policy=none
-prefetch_cache_check_push=true
-prefetch_use_cpu_id=true
-prefetch_data_accesses_only=false
-hit_latency=1
-
-[stats]
-descriptions=true
-project_name=test
-simulation_name=test
-simulation_sample=0
-text_file=m5stats.txt
-text_compat=true
-mysql_db=
-mysql_user=
-mysql_password=
-mysql_host=
-events_start=-1
-dump_reset=false
-dump_cycle=0
-dump_period=0
-ignore_events=
-
-[statsreset]
-reset_cycle=0
-
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
deleted file mode 100644 (file)
index 45f793a..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/m5stats.txt
+++ /dev/null
@@ -1,220 +0,0 @@
-
----------- Begin Simulation Statistics ----------
-host_inst_rate                                 752631                       # Simulator instruction rate (inst/s)
-host_mem_usage                                 230876                       # Number of bytes of host memory used
-host_seconds                                  2669.29                       # Real time elapsed on the host
-host_tick_rate                                2836913                       # Simulator tick rate (ticks/s)
-sim_freq                                 1000000000000                       # Frequency of simulated ticks
-sim_insts                                  2008987607                       # Number of instructions simulated
-sim_seconds                                  0.007573                       # Number of seconds simulated
-sim_ticks                                  7572532003                       # Number of ticks simulated
-system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
-system.cpu.dcache.ReadReq_avg_miss_latency  3107.171986                       # average ReadReq miss latency
-system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2107.171986                       # average ReadReq mshr miss latency
-system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
-system.cpu.dcache.ReadReq_miss_latency     4530853333                       # number of ReadReq miss cycles
-system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
-system.cpu.dcache.ReadReq_mshr_miss_latency   3072661333                       # number of ReadReq MSHR miss cycles
-system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
-system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
-system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
-system.cpu.dcache.WriteReq_avg_miss_latency  3884.267929                       # average WriteReq miss latency
-system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2884.267929                       # average WriteReq mshr miss latency
-system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
-system.cpu.dcache.WriteReq_miss_latency     279480846                       # number of WriteReq miss cycles
-system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
-system.cpu.dcache.WriteReq_mshr_miss_latency    207528846                       # number of WriteReq MSHR miss cycles
-system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
-system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
-system.cpu.dcache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
-system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
-system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
-system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
-system.cpu.dcache.demand_avg_miss_latency  3143.713388                       # average overall miss latency
-system.cpu.dcache.demand_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
-system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
-system.cpu.dcache.demand_miss_latency      4810334179                       # number of demand (read+write) miss cycles
-system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
-system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
-system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.dcache.demand_mshr_miss_latency   3280190179                       # number of demand (read+write) MSHR miss cycles
-system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
-system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
-system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
-system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
-system.cpu.dcache.overall_avg_miss_latency  3143.713388                       # average overall miss latency
-system.cpu.dcache.overall_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
-system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
-system.cpu.dcache.overall_hits              720334778                       # number of overall hits
-system.cpu.dcache.overall_miss_latency     4810334179                       # number of overall miss cycles
-system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
-system.cpu.dcache.overall_misses              1530144                       # number of overall misses
-system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.dcache.overall_mshr_miss_latency   3280190179                       # number of overall MSHR miss cycles
-system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
-system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
-system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.dcache.replacements                1526048                       # number of replacements
-system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
-system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.dcache.tagsinuse               4087.479154                       # Cycle average of tags in use
-system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
-system.cpu.dcache.warmup_cycle               35165000                       # Cycle when the warmup percentage was hit.
-system.cpu.dcache.writebacks                    74589                       # number of writebacks
-system.cpu.icache.ReadReq_accesses         2008987608                       # number of ReadReq accesses(hits+misses)
-system.cpu.icache.ReadReq_avg_miss_latency  3103.627312                       # average ReadReq miss latency
-system.cpu.icache.ReadReq_avg_mshr_miss_latency  2103.627312                       # average ReadReq mshr miss latency
-system.cpu.icache.ReadReq_hits             2008977012                       # number of ReadReq hits
-system.cpu.icache.ReadReq_miss_latency       32886035                       # number of ReadReq miss cycles
-system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
-system.cpu.icache.ReadReq_mshr_miss_latency     22290035                       # number of ReadReq MSHR miss cycles
-system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
-system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
-system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
-system.cpu.icache.avg_refs               189597.679502                       # Average number of references to valid blocks.
-system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
-system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.icache.cache_copies                      0                       # number of cache copies performed
-system.cpu.icache.demand_accesses          2008987608                       # number of demand (read+write) accesses
-system.cpu.icache.demand_avg_miss_latency  3103.627312                       # average overall miss latency
-system.cpu.icache.demand_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
-system.cpu.icache.demand_hits              2008977012                       # number of demand (read+write) hits
-system.cpu.icache.demand_miss_latency        32886035                       # number of demand (read+write) miss cycles
-system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
-system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
-system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
-system.cpu.icache.demand_mshr_miss_latency     22290035                       # number of demand (read+write) MSHR miss cycles
-system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
-system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
-system.cpu.icache.fast_writes                       0                       # number of fast writes performed
-system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
-system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
-system.cpu.icache.overall_accesses         2008987608                       # number of overall (read+write) accesses
-system.cpu.icache.overall_avg_miss_latency  3103.627312                       # average overall miss latency
-system.cpu.icache.overall_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
-system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
-system.cpu.icache.overall_hits             2008977012                       # number of overall hits
-system.cpu.icache.overall_miss_latency       32886035                       # number of overall miss cycles
-system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
-system.cpu.icache.overall_misses                10596                       # number of overall misses
-system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
-system.cpu.icache.overall_mshr_miss_latency     22290035                       # number of overall MSHR miss cycles
-system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
-system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
-system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.icache.replacements                   9046                       # number of replacements
-system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
-system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.icache.tagsinuse               1471.254279                       # Cycle average of tags in use
-system.cpu.icache.total_refs               2008977012                       # Total number of references to valid blocks.
-system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
-system.cpu.icache.writebacks                        0                       # number of writebacks
-system.cpu.idle_fraction                            0                       # Percentage of idle cycles
-system.cpu.l2cache.ReadReq_accesses           1540740                       # number of ReadReq accesses(hits+misses)
-system.cpu.l2cache.ReadReq_avg_miss_latency  2153.828221                       # average ReadReq miss latency
-system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1111.659139                       # average ReadReq mshr miss latency
-system.cpu.l2cache.ReadReq_hits                 33878                       # number of ReadReq hits
-system.cpu.l2cache.ReadReq_miss_latency    3245521901                       # number of ReadReq miss cycles
-system.cpu.l2cache.ReadReq_miss_rate         0.978012                       # miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_misses             1506862                       # number of ReadReq misses
-system.cpu.l2cache.ReadReq_mshr_miss_latency   1675116913                       # number of ReadReq MSHR miss cycles
-system.cpu.l2cache.ReadReq_mshr_miss_rate     0.978012                       # mshr miss rate for ReadReq accesses
-system.cpu.l2cache.ReadReq_mshr_misses        1506862                       # number of ReadReq MSHR misses
-system.cpu.l2cache.Writeback_accesses           74589                       # number of Writeback accesses(hits+misses)
-system.cpu.l2cache.Writeback_hits               73515                       # number of Writeback hits
-system.cpu.l2cache.Writeback_miss_rate       0.014399                       # miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_misses              1074                       # number of Writeback misses
-system.cpu.l2cache.Writeback_mshr_miss_rate     0.014399                       # mshr miss rate for Writeback accesses
-system.cpu.l2cache.Writeback_mshr_misses         1074                       # number of Writeback MSHR misses
-system.cpu.l2cache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
-system.cpu.l2cache.avg_refs                  0.071269                       # Average number of references to valid blocks.
-system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
-system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
-system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
-system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
-system.cpu.l2cache.demand_avg_miss_latency  2153.828221                       # average overall miss latency
-system.cpu.l2cache.demand_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
-system.cpu.l2cache.demand_hits                  33878                       # number of demand (read+write) hits
-system.cpu.l2cache.demand_miss_latency     3245521901                       # number of demand (read+write) miss cycles
-system.cpu.l2cache.demand_miss_rate          0.978012                       # miss rate for demand accesses
-system.cpu.l2cache.demand_misses              1506862                       # number of demand (read+write) misses
-system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
-system.cpu.l2cache.demand_mshr_miss_latency   1675116913                       # number of demand (read+write) MSHR miss cycles
-system.cpu.l2cache.demand_mshr_miss_rate     0.978012                       # mshr miss rate for demand accesses
-system.cpu.l2cache.demand_mshr_misses         1506862                       # number of demand (read+write) MSHR misses
-system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
-system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
-system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
-system.cpu.l2cache.overall_accesses           1615329                       # number of overall (read+write) accesses
-system.cpu.l2cache.overall_avg_miss_latency  2152.294196                       # average overall miss latency
-system.cpu.l2cache.overall_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
-system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
-system.cpu.l2cache.overall_hits                107393                       # number of overall hits
-system.cpu.l2cache.overall_miss_latency    3245521901                       # number of overall miss cycles
-system.cpu.l2cache.overall_miss_rate         0.933516                       # miss rate for overall accesses
-system.cpu.l2cache.overall_misses             1507936                       # number of overall misses
-system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
-system.cpu.l2cache.overall_mshr_miss_latency   1675116913                       # number of overall MSHR miss cycles
-system.cpu.l2cache.overall_mshr_miss_rate     0.932851                       # mshr miss rate for overall accesses
-system.cpu.l2cache.overall_mshr_misses        1506862                       # number of overall MSHR misses
-system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
-system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
-system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
-system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
-system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
-system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
-system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
-system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
-system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
-system.cpu.l2cache.replacements               1474094                       # number of replacements
-system.cpu.l2cache.sampled_refs               1506862                       # Sample count of references to valid blocks.
-system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
-system.cpu.l2cache.tagsinuse             32444.706916                       # Cycle average of tags in use
-system.cpu.l2cache.total_refs                  107393                       # Total number of references to valid blocks.
-system.cpu.l2cache.warmup_cycle             164189000                       # Cycle when the warmup percentage was hit.
-system.cpu.l2cache.writebacks                   66804                       # number of writebacks
-system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
-system.cpu.numCycles                       7572532003                       # number of cpu cycles simulated
-system.cpu.num_insts                       2008987607                       # Number of instructions executed
-system.cpu.num_refs                         722390435                       # Number of memory references
-system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
-
----------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
deleted file mode 100644 (file)
index bc72461..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stderr
+++ /dev/null
@@ -1,3 +0,0 @@
-0: system.remote_gdb.listener: listening for remote gdb on port 7000
-warn: Entering event queue @ 0.  Starting simulation...
-warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
deleted file mode 100644 (file)
index d4a078b..0000000
--- a/tests/long/40.perlbmk/ref/alpha/linux/simple-timing/stdout
+++ /dev/null
@@ -1,1376 +0,0 @@
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diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
new file mode 100644 (file)
index 0000000..59c6e25
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.ini
@@ -0,0 +1,90 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=AtomicSimpleCPU
+children=workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+simulate_stalls=false
+system=system
+width=1
+workload=system.cpu.workload
+dcache_port=system.membus.port[2]
+icache_port=system.membus.port[1]
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
new file mode 100644 (file)
index 0000000..c6e4aa1
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/config.out
@@ -0,0 +1,80 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=AtomicSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+width=1
+function_trace=false
+function_trace_start=0
+simulate_stalls=false
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
new file mode 100644 (file)
index 0000000..9db3f64
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/m5stats.txt
@@ -0,0 +1,18 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                1149393                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 177516                       # Number of bytes of host memory used
+host_seconds                                  1747.87                       # Real time elapsed on the host
+host_tick_rate                                1149393                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  2008987607                       # Number of instructions simulated
+sim_seconds                                  0.002009                       # Number of seconds simulated
+sim_ticks                                  2008987606                       # Number of ticks simulated
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                       2008987607                       # number of cpu cycles simulated
+system.cpu.num_insts                       2008987607                       # Number of instructions executed
+system.cpu.num_refs                         722390435                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
new file mode 100644 (file)
index 0000000..bc72461
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stderr
@@ -0,0 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
+warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
new file mode 100644 (file)
index 0000000..d4a078b
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-atomic/stdout
@@ -0,0 +1,1376 @@
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diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
new file mode 100644 (file)
index 0000000..5f64dce
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.ini
@@ -0,0 +1,213 @@
+[root]
+type=Root
+children=system
+checkpoint=
+clock=1000000000000
+max_tick=0
+output_file=cout
+progress_interval=0
+
+[serialize]
+count=10
+cycle=0
+dir=cpt.%012d
+period=0
+
+[stats]
+descriptions=true
+dump_cycle=0
+dump_period=0
+dump_reset=false
+ignore_events=
+mysql_db=
+mysql_host=
+mysql_password=
+mysql_user=
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_compat=true
+text_file=m5stats.txt
+
+[system]
+type=System
+children=cpu membus physmem
+mem_mode=atomic
+physmem=system.physmem
+
+[system.cpu]
+type=TimingSimpleCPU
+children=dcache icache l2cache toL2Bus workload
+clock=1
+cpu_id=0
+defer_registration=false
+function_trace=false
+function_trace_start=0
+max_insts_all_threads=0
+max_insts_any_thread=0
+max_loads_all_threads=0
+max_loads_any_thread=0
+phase=0
+progress_interval=0
+system=system
+workload=system.cpu.workload
+dcache_port=system.cpu.dcache.cpu_side
+icache_port=system.cpu.icache.cpu_side
+
+[system.cpu.dcache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=262144
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.dcache_port
+mem_side=system.cpu.toL2Bus.port[1]
+
+[system.cpu.icache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=131072
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.icache_port
+mem_side=system.cpu.toL2Bus.port[0]
+
+[system.cpu.l2cache]
+type=BaseCache
+adaptive_compression=false
+assoc=2
+block_size=64
+compressed_bus=false
+compression_latency=0
+hash_delay=1
+hit_latency=1
+latency=1
+lifo=false
+max_miss_count=0
+mshrs=10
+prefetch_access=false
+prefetch_cache_check_push=true
+prefetch_data_accesses_only=false
+prefetch_degree=1
+prefetch_latency=10
+prefetch_miss=false
+prefetch_past_page=false
+prefetch_policy=none
+prefetch_serial_squash=false
+prefetch_use_cpu_id=true
+prefetcher_size=100
+prioritizeRequests=false
+protocol=Null
+repl=Null
+size=2097152
+split=false
+split_size=0
+store_compressed=false
+subblock_size=0
+tgts_per_mshr=5
+trace_addr=0
+two_queue=false
+write_buffers=8
+cpu_side=system.cpu.toL2Bus.port[2]
+mem_side=system.membus.port[1]
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+egid=100
+env=
+euid=100
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+gid=100
+input=cin
+output=cout
+pid=100
+ppid=99
+system=system
+uid=100
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+responder_set=false
+width=64
+port=system.physmem.port system.cpu.l2cache.mem_side
+
+[system.physmem]
+type=PhysicalMemory
+file=
+latency=1
+range=0:134217727
+zero=false
+port=system.membus.port[0]
+
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
new file mode 100644 (file)
index 0000000..6998f48
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/config.out
@@ -0,0 +1,201 @@
+[root]
+type=Root
+clock=1000000000000
+max_tick=0
+progress_interval=0
+output_file=cout
+
+[system.physmem]
+type=PhysicalMemory
+file=
+range=[0,134217727]
+latency=1
+zero=false
+
+[system]
+type=System
+physmem=system.physmem
+mem_mode=atomic
+
+[system.membus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.workload]
+type=LiveProcess
+cmd=perlbmk -I. -I lib lgred.makerand.pl
+executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
+input=cin
+output=cout
+env=
+cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
+system=system
+uid=100
+euid=100
+gid=100
+egid=100
+pid=100
+ppid=99
+
+[system.cpu]
+type=TimingSimpleCPU
+max_insts_any_thread=0
+max_insts_all_threads=0
+max_loads_any_thread=0
+max_loads_all_threads=0
+progress_interval=0
+system=system
+cpu_id=0
+workload=system.cpu.workload
+clock=1
+phase=0
+defer_registration=false
+// width not specified
+function_trace=false
+function_trace_start=0
+// simulate_stalls not specified
+
+[system.cpu.toL2Bus]
+type=Bus
+bus_id=0
+clock=1000
+width=64
+responder_set=false
+
+[system.cpu.icache]
+type=BaseCache
+size=131072
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.dcache]
+type=BaseCache
+size=262144
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[system.cpu.l2cache]
+type=BaseCache
+size=2097152
+assoc=2
+block_size=64
+latency=1
+mshrs=10
+tgts_per_mshr=5
+write_buffers=8
+prioritizeRequests=false
+protocol=null
+trace_addr=0
+hash_delay=1
+repl=null
+compressed_bus=false
+store_compressed=false
+adaptive_compression=false
+compression_latency=0
+block_size=64
+max_miss_count=0
+addr_range=[0,18446744073709551615]
+split=false
+split_size=0
+lifo=false
+two_queue=false
+prefetch_miss=false
+prefetch_access=false
+prefetcher_size=100
+prefetch_past_page=false
+prefetch_serial_squash=false
+prefetch_latency=10
+prefetch_degree=1
+prefetch_policy=none
+prefetch_cache_check_push=true
+prefetch_use_cpu_id=true
+prefetch_data_accesses_only=false
+hit_latency=1
+
+[stats]
+descriptions=true
+project_name=test
+simulation_name=test
+simulation_sample=0
+text_file=m5stats.txt
+text_compat=true
+mysql_db=
+mysql_user=
+mysql_password=
+mysql_host=
+events_start=-1
+dump_reset=false
+dump_cycle=0
+dump_period=0
+ignore_events=
+
+[statsreset]
+reset_cycle=0
+
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
new file mode 100644 (file)
index 0000000..45f793a
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/m5stats.txt
@@ -0,0 +1,220 @@
+
+---------- Begin Simulation Statistics ----------
+host_inst_rate                                 752631                       # Simulator instruction rate (inst/s)
+host_mem_usage                                 230876                       # Number of bytes of host memory used
+host_seconds                                  2669.29                       # Real time elapsed on the host
+host_tick_rate                                2836913                       # Simulator tick rate (ticks/s)
+sim_freq                                 1000000000000                       # Frequency of simulated ticks
+sim_insts                                  2008987607                       # Number of instructions simulated
+sim_seconds                                  0.007573                       # Number of seconds simulated
+sim_ticks                                  7572532003                       # Number of ticks simulated
+system.cpu.dcache.ReadReq_accesses          511070026                       # number of ReadReq accesses(hits+misses)
+system.cpu.dcache.ReadReq_avg_miss_latency  3107.171986                       # average ReadReq miss latency
+system.cpu.dcache.ReadReq_avg_mshr_miss_latency  2107.171986                       # average ReadReq mshr miss latency
+system.cpu.dcache.ReadReq_hits              509611834                       # number of ReadReq hits
+system.cpu.dcache.ReadReq_miss_latency     4530853333                       # number of ReadReq miss cycles
+system.cpu.dcache.ReadReq_miss_rate          0.002853                       # miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_misses              1458192                       # number of ReadReq misses
+system.cpu.dcache.ReadReq_mshr_miss_latency   3072661333                       # number of ReadReq MSHR miss cycles
+system.cpu.dcache.ReadReq_mshr_miss_rate     0.002853                       # mshr miss rate for ReadReq accesses
+system.cpu.dcache.ReadReq_mshr_misses         1458192                       # number of ReadReq MSHR misses
+system.cpu.dcache.WriteReq_accesses         210794896                       # number of WriteReq accesses(hits+misses)
+system.cpu.dcache.WriteReq_avg_miss_latency  3884.267929                       # average WriteReq miss latency
+system.cpu.dcache.WriteReq_avg_mshr_miss_latency  2884.267929                       # average WriteReq mshr miss latency
+system.cpu.dcache.WriteReq_hits             210722944                       # number of WriteReq hits
+system.cpu.dcache.WriteReq_miss_latency     279480846                       # number of WriteReq miss cycles
+system.cpu.dcache.WriteReq_miss_rate         0.000341                       # miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_misses               71952                       # number of WriteReq misses
+system.cpu.dcache.WriteReq_mshr_miss_latency    207528846                       # number of WriteReq MSHR miss cycles
+system.cpu.dcache.WriteReq_mshr_miss_rate     0.000341                       # mshr miss rate for WriteReq accesses
+system.cpu.dcache.WriteReq_mshr_misses          71952                       # number of WriteReq MSHR misses
+system.cpu.dcache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.dcache.avg_refs                 470.762737                       # Average number of references to valid blocks.
+system.cpu.dcache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.dcache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.dcache.cache_copies                      0                       # number of cache copies performed
+system.cpu.dcache.demand_accesses           721864922                       # number of demand (read+write) accesses
+system.cpu.dcache.demand_avg_miss_latency  3143.713388                       # average overall miss latency
+system.cpu.dcache.demand_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
+system.cpu.dcache.demand_hits               720334778                       # number of demand (read+write) hits
+system.cpu.dcache.demand_miss_latency      4810334179                       # number of demand (read+write) miss cycles
+system.cpu.dcache.demand_miss_rate           0.002120                       # miss rate for demand accesses
+system.cpu.dcache.demand_misses               1530144                       # number of demand (read+write) misses
+system.cpu.dcache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.dcache.demand_mshr_miss_latency   3280190179                       # number of demand (read+write) MSHR miss cycles
+system.cpu.dcache.demand_mshr_miss_rate      0.002120                       # mshr miss rate for demand accesses
+system.cpu.dcache.demand_mshr_misses          1530144                       # number of demand (read+write) MSHR misses
+system.cpu.dcache.fast_writes                       0                       # number of fast writes performed
+system.cpu.dcache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.dcache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.dcache.overall_accesses          721864922                       # number of overall (read+write) accesses
+system.cpu.dcache.overall_avg_miss_latency  3143.713388                       # average overall miss latency
+system.cpu.dcache.overall_avg_mshr_miss_latency  2143.713388                       # average overall mshr miss latency
+system.cpu.dcache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.dcache.overall_hits              720334778                       # number of overall hits
+system.cpu.dcache.overall_miss_latency     4810334179                       # number of overall miss cycles
+system.cpu.dcache.overall_miss_rate          0.002120                       # miss rate for overall accesses
+system.cpu.dcache.overall_misses              1530144                       # number of overall misses
+system.cpu.dcache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.dcache.overall_mshr_miss_latency   3280190179                       # number of overall MSHR miss cycles
+system.cpu.dcache.overall_mshr_miss_rate     0.002120                       # mshr miss rate for overall accesses
+system.cpu.dcache.overall_mshr_misses         1530144                       # number of overall MSHR misses
+system.cpu.dcache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.dcache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.dcache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.dcache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.dcache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.dcache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.dcache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.dcache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.dcache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.dcache.replacements                1526048                       # number of replacements
+system.cpu.dcache.sampled_refs                1530144                       # Sample count of references to valid blocks.
+system.cpu.dcache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.dcache.tagsinuse               4087.479154                       # Cycle average of tags in use
+system.cpu.dcache.total_refs                720334778                       # Total number of references to valid blocks.
+system.cpu.dcache.warmup_cycle               35165000                       # Cycle when the warmup percentage was hit.
+system.cpu.dcache.writebacks                    74589                       # number of writebacks
+system.cpu.icache.ReadReq_accesses         2008987608                       # number of ReadReq accesses(hits+misses)
+system.cpu.icache.ReadReq_avg_miss_latency  3103.627312                       # average ReadReq miss latency
+system.cpu.icache.ReadReq_avg_mshr_miss_latency  2103.627312                       # average ReadReq mshr miss latency
+system.cpu.icache.ReadReq_hits             2008977012                       # number of ReadReq hits
+system.cpu.icache.ReadReq_miss_latency       32886035                       # number of ReadReq miss cycles
+system.cpu.icache.ReadReq_miss_rate          0.000005                       # miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_misses                10596                       # number of ReadReq misses
+system.cpu.icache.ReadReq_mshr_miss_latency     22290035                       # number of ReadReq MSHR miss cycles
+system.cpu.icache.ReadReq_mshr_miss_rate     0.000005                       # mshr miss rate for ReadReq accesses
+system.cpu.icache.ReadReq_mshr_misses           10596                       # number of ReadReq MSHR misses
+system.cpu.icache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.icache.avg_refs               189597.679502                       # Average number of references to valid blocks.
+system.cpu.icache.blocked_no_mshrs                  0                       # number of cycles access was blocked
+system.cpu.icache.blocked_no_targets                0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.icache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.icache.cache_copies                      0                       # number of cache copies performed
+system.cpu.icache.demand_accesses          2008987608                       # number of demand (read+write) accesses
+system.cpu.icache.demand_avg_miss_latency  3103.627312                       # average overall miss latency
+system.cpu.icache.demand_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
+system.cpu.icache.demand_hits              2008977012                       # number of demand (read+write) hits
+system.cpu.icache.demand_miss_latency        32886035                       # number of demand (read+write) miss cycles
+system.cpu.icache.demand_miss_rate           0.000005                       # miss rate for demand accesses
+system.cpu.icache.demand_misses                 10596                       # number of demand (read+write) misses
+system.cpu.icache.demand_mshr_hits                  0                       # number of demand (read+write) MSHR hits
+system.cpu.icache.demand_mshr_miss_latency     22290035                       # number of demand (read+write) MSHR miss cycles
+system.cpu.icache.demand_mshr_miss_rate      0.000005                       # mshr miss rate for demand accesses
+system.cpu.icache.demand_mshr_misses            10596                       # number of demand (read+write) MSHR misses
+system.cpu.icache.fast_writes                       0                       # number of fast writes performed
+system.cpu.icache.mshr_cap_events                   0                       # number of times MSHR cap was activated
+system.cpu.icache.no_allocate_misses                0                       # Number of misses that were no-allocate
+system.cpu.icache.overall_accesses         2008987608                       # number of overall (read+write) accesses
+system.cpu.icache.overall_avg_miss_latency  3103.627312                       # average overall miss latency
+system.cpu.icache.overall_avg_mshr_miss_latency  2103.627312                       # average overall mshr miss latency
+system.cpu.icache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.icache.overall_hits             2008977012                       # number of overall hits
+system.cpu.icache.overall_miss_latency       32886035                       # number of overall miss cycles
+system.cpu.icache.overall_miss_rate          0.000005                       # miss rate for overall accesses
+system.cpu.icache.overall_misses                10596                       # number of overall misses
+system.cpu.icache.overall_mshr_hits                 0                       # number of overall MSHR hits
+system.cpu.icache.overall_mshr_miss_latency     22290035                       # number of overall MSHR miss cycles
+system.cpu.icache.overall_mshr_miss_rate     0.000005                       # mshr miss rate for overall accesses
+system.cpu.icache.overall_mshr_misses           10596                       # number of overall MSHR misses
+system.cpu.icache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.icache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.icache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.icache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.icache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.icache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.icache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.icache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.icache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.icache.replacements                   9046                       # number of replacements
+system.cpu.icache.sampled_refs                  10596                       # Sample count of references to valid blocks.
+system.cpu.icache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.icache.tagsinuse               1471.254279                       # Cycle average of tags in use
+system.cpu.icache.total_refs               2008977012                       # Total number of references to valid blocks.
+system.cpu.icache.warmup_cycle                      0                       # Cycle when the warmup percentage was hit.
+system.cpu.icache.writebacks                        0                       # number of writebacks
+system.cpu.idle_fraction                            0                       # Percentage of idle cycles
+system.cpu.l2cache.ReadReq_accesses           1540740                       # number of ReadReq accesses(hits+misses)
+system.cpu.l2cache.ReadReq_avg_miss_latency  2153.828221                       # average ReadReq miss latency
+system.cpu.l2cache.ReadReq_avg_mshr_miss_latency  1111.659139                       # average ReadReq mshr miss latency
+system.cpu.l2cache.ReadReq_hits                 33878                       # number of ReadReq hits
+system.cpu.l2cache.ReadReq_miss_latency    3245521901                       # number of ReadReq miss cycles
+system.cpu.l2cache.ReadReq_miss_rate         0.978012                       # miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_misses             1506862                       # number of ReadReq misses
+system.cpu.l2cache.ReadReq_mshr_miss_latency   1675116913                       # number of ReadReq MSHR miss cycles
+system.cpu.l2cache.ReadReq_mshr_miss_rate     0.978012                       # mshr miss rate for ReadReq accesses
+system.cpu.l2cache.ReadReq_mshr_misses        1506862                       # number of ReadReq MSHR misses
+system.cpu.l2cache.Writeback_accesses           74589                       # number of Writeback accesses(hits+misses)
+system.cpu.l2cache.Writeback_hits               73515                       # number of Writeback hits
+system.cpu.l2cache.Writeback_miss_rate       0.014399                       # miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_misses              1074                       # number of Writeback misses
+system.cpu.l2cache.Writeback_mshr_miss_rate     0.014399                       # mshr miss rate for Writeback accesses
+system.cpu.l2cache.Writeback_mshr_misses         1074                       # number of Writeback MSHR misses
+system.cpu.l2cache.avg_blocked_cycles_no_mshrs     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_blocked_cycles_no_targets     no value                       # average number of cycles each access was blocked
+system.cpu.l2cache.avg_refs                  0.071269                       # Average number of references to valid blocks.
+system.cpu.l2cache.blocked_no_mshrs                 0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_no_targets               0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_mshrs            0                       # number of cycles access was blocked
+system.cpu.l2cache.blocked_cycles_no_targets            0                       # number of cycles access was blocked
+system.cpu.l2cache.cache_copies                     0                       # number of cache copies performed
+system.cpu.l2cache.demand_accesses            1540740                       # number of demand (read+write) accesses
+system.cpu.l2cache.demand_avg_miss_latency  2153.828221                       # average overall miss latency
+system.cpu.l2cache.demand_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
+system.cpu.l2cache.demand_hits                  33878                       # number of demand (read+write) hits
+system.cpu.l2cache.demand_miss_latency     3245521901                       # number of demand (read+write) miss cycles
+system.cpu.l2cache.demand_miss_rate          0.978012                       # miss rate for demand accesses
+system.cpu.l2cache.demand_misses              1506862                       # number of demand (read+write) misses
+system.cpu.l2cache.demand_mshr_hits                 0                       # number of demand (read+write) MSHR hits
+system.cpu.l2cache.demand_mshr_miss_latency   1675116913                       # number of demand (read+write) MSHR miss cycles
+system.cpu.l2cache.demand_mshr_miss_rate     0.978012                       # mshr miss rate for demand accesses
+system.cpu.l2cache.demand_mshr_misses         1506862                       # number of demand (read+write) MSHR misses
+system.cpu.l2cache.fast_writes                      0                       # number of fast writes performed
+system.cpu.l2cache.mshr_cap_events                  0                       # number of times MSHR cap was activated
+system.cpu.l2cache.no_allocate_misses               0                       # Number of misses that were no-allocate
+system.cpu.l2cache.overall_accesses           1615329                       # number of overall (read+write) accesses
+system.cpu.l2cache.overall_avg_miss_latency  2152.294196                       # average overall miss latency
+system.cpu.l2cache.overall_avg_mshr_miss_latency  1111.659139                       # average overall mshr miss latency
+system.cpu.l2cache.overall_avg_mshr_uncacheable_latency     no value                       # average overall mshr uncacheable latency
+system.cpu.l2cache.overall_hits                107393                       # number of overall hits
+system.cpu.l2cache.overall_miss_latency    3245521901                       # number of overall miss cycles
+system.cpu.l2cache.overall_miss_rate         0.933516                       # miss rate for overall accesses
+system.cpu.l2cache.overall_misses             1507936                       # number of overall misses
+system.cpu.l2cache.overall_mshr_hits                0                       # number of overall MSHR hits
+system.cpu.l2cache.overall_mshr_miss_latency   1675116913                       # number of overall MSHR miss cycles
+system.cpu.l2cache.overall_mshr_miss_rate     0.932851                       # mshr miss rate for overall accesses
+system.cpu.l2cache.overall_mshr_misses        1506862                       # number of overall MSHR misses
+system.cpu.l2cache.overall_mshr_uncacheable_latency            0                       # number of overall MSHR uncacheable cycles
+system.cpu.l2cache.overall_mshr_uncacheable_misses            0                       # number of overall MSHR uncacheable misses
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache            0                       # number of hwpf that were already in the cache
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_mshr            0                       # number of hwpf that were already in mshr
+system.cpu.l2cache.prefetcher.num_hwpf_already_in_prefetcher            0                       # number of hwpf that were already in the prefetch queue
+system.cpu.l2cache.prefetcher.num_hwpf_evicted            0                       # number of hwpf removed due to no buffer left
+system.cpu.l2cache.prefetcher.num_hwpf_identified            0                       # number of hwpf identified
+system.cpu.l2cache.prefetcher.num_hwpf_issued            0                       # number of hwpf issued
+system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit            0                       # number of hwpf removed because MSHR allocated
+system.cpu.l2cache.prefetcher.num_hwpf_span_page            0                       # number of hwpf spanning a virtual page
+system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss            0                       # number of hwpf that got squashed due to a miss aborting calculation time
+system.cpu.l2cache.replacements               1474094                       # number of replacements
+system.cpu.l2cache.sampled_refs               1506862                       # Sample count of references to valid blocks.
+system.cpu.l2cache.soft_prefetch_mshr_full            0                       # number of mshr full events for SW prefetching instrutions
+system.cpu.l2cache.tagsinuse             32444.706916                       # Cycle average of tags in use
+system.cpu.l2cache.total_refs                  107393                       # Total number of references to valid blocks.
+system.cpu.l2cache.warmup_cycle             164189000                       # Cycle when the warmup percentage was hit.
+system.cpu.l2cache.writebacks                   66804                       # number of writebacks
+system.cpu.not_idle_fraction                        1                       # Percentage of non-idle cycles
+system.cpu.numCycles                       7572532003                       # number of cpu cycles simulated
+system.cpu.num_insts                       2008987607                       # Number of instructions executed
+system.cpu.num_refs                         722390435                       # Number of memory references
+system.cpu.workload.PROG:num_syscalls              39                       # Number of system calls
+
+---------- End Simulation Statistics   ----------
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
new file mode 100644 (file)
index 0000000..bc72461
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stderr
@@ -0,0 +1,3 @@
+0: system.remote_gdb.listener: listening for remote gdb on port 7000
+warn: Entering event queue @ 0.  Starting simulation...
+warn: ignoring syscall sigprocmask(1, 0, ...)
diff --git a/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
new file mode 100644 (file)
index 0000000..d4a078b
--- /dev/null
+++ b/tests/long/40.perlbmk/ref/alpha/tru64/simple-timing/stdout
@@ -0,0 +1,1376 @@
+1375000: 2038431008
+1374000: 3487365506
+1373000: 4184770123
+1372000: 1943746837
+1371000: 2651673663
+1370000: 1493817016
+1369000: 2894014801
+1368000: 1932092157
+1367000: 1670009799
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