sim: mips: delete mmu stubs to move to common sim_{read,write}

The only unique thing about mip's sim_{read,write} helpers is the call to
address_translation on the incoming address.  When we look closer at that
function though, we see it's just a stub that maps physical to virtual,
and the cache/return values are hardcoded.  If we delete this function,
we can then collapse all the callers and drop the custom sim_{read,write}
logic entirely.

Some day we might want to add MMU support, but when we do, we'll want to
have the common layers handle things so all targets benefit.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 46fd20c6ca5708ad2609b7fe67694ea539596bd5..eb076e460c2b3ebf634f46885a69937720136a49 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,22 @@
+2015-12-26  Mike Frysinger  <vapier@gentoo.org>
+
+       * interp.c (sim_write, sim_read): Delete.
+       (store_word): Delete call to AddressTranslation and set paddr=vaddr.
+       (load_word): Likewise.
+       * micromips.igen (cache): Likewise.
+       * mips.igen (do_ll, do_lld, do_sc, do_scd, do_suxc1_32, do_swc1,
+       do_swxc1, cache, do_load, do_load_left, do_load_right, do_store,
+       do_store_left, do_store_right, do_load_double, do_store_double):
+       Likewise.
+       (do_pref): Delete call to AddressTranslation and stub out Prefetch.
+       (do_prefx): Likewise.
+       * sim-main.c (address_translation, prefetch): Delete.
+       (ifetch32, ifetch16): Delete call to AddressTranslation and set
+       paddr=vaddr.
+       * sim-main.h (Uncached, CachedNoncoherent, CachedCoherent, Cached,
+       address_translation, AddressTranslation, prefetch, Prefetch): Delete.
+       (LoadMemory, StoreMemory): Delete CCA arg.
+
 2015-12-24  Mike Frysinger  <vapier@gentoo.org>
 
        * configure.ac (SIM_SUBTARGET): Drop -DTARGET_TX3904=1.

diff --git a/sim/mips/interp.c b/sim/mips/interp.c
index 524f5bec8e46235138dbbc2bd365dc40a2087011..0ca6f1aef205646591080463865e18af7342ff25 100644 (file)
--- a/sim/mips/interp.c
+++ b/sim/mips/interp.c
@@ -840,59 +840,6 @@ mips_sim_close (SIM_DESC sd, int quitting)
 #endif
 }
 
-int
-sim_write (SIM_DESC sd, SIM_ADDR addr, const unsigned char *buffer, int size)
-{
-  int index;
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
-  /* Return the number of bytes written, or zero if error. */
-#ifdef DEBUG
-  sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
-#endif
-
-  /* We use raw read and write routines, since we do not want to count
-     the GDB memory accesses in our statistics gathering. */
-
-  for (index = 0; index < size; index++)
-    {
-      address_word vaddr = (address_word)addr + index;
-      address_word paddr;
-      int cca;
-      if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
-       break;
-      if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
-       break;
-    }
-
-  return(index);
-}
-
-int
-sim_read (SIM_DESC sd, SIM_ADDR addr, unsigned char *buffer, int size)
-{
-  int index;
-  sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
-  /* Return the number of bytes read, or zero if error. */
-#ifdef DEBUG
-  sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
-#endif /* DEBUG */
-
-  for (index = 0; (index < size); index++)
-    {
-      address_word vaddr = (address_word)addr + index;
-      address_word paddr;
-      int cca;
-      if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
-       break;
-      if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
-       break;
-    }
-
-  return(index);
-}
-
 int
 sim_store_register (SIM_DESC sd, int rn, unsigned char *memory, int length)
 {
@@ -1491,26 +1438,21 @@ store_word (SIM_DESC sd,
            uword64 vaddr,
            signed_word val)
 {
-  address_word paddr;
-  int uncached;
+  address_word paddr = vaddr;
 
   if ((vaddr & 3) != 0)
     SignalExceptionAddressStore ();
   else
     {
-      if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-                             isTARGET, isREAL))
-       {
-         const uword64 mask = 7;
-         uword64 memval;
-         unsigned int byte;
-
-         paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
-         byte = (vaddr & mask) ^ (BigEndianCPU << 2);
-         memval = ((uword64) val) << (8 * byte);
-         StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
-                      isREAL);
-       }
+      const uword64 mask = 7;
+      uword64 memval;
+      unsigned int byte;
+
+      paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+      byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+      memval = ((uword64) val) << (8 * byte);
+      StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
+                  isREAL);
     }
 }
 
@@ -1528,24 +1470,18 @@ load_word (SIM_DESC sd,
     }
   else
     {
-      address_word paddr;
-      int uncached;
-
-      if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-                             isTARGET, isREAL))
-       {
-         const uword64 mask = 0x7;
-         const unsigned int reverse = ReverseEndian ? 1 : 0;
-         const unsigned int bigend = BigEndianCPU ? 1 : 0;
-         uword64 memval;
-         unsigned int byte;
-
-         paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
-         LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
-                              isDATA, isREAL);
-         byte = (vaddr & mask) ^ (bigend << 2);
-         return EXTEND32 (memval >> (8 * byte));
-       }
+      address_word paddr = vaddr;
+      const uword64 mask = 0x7;
+      const unsigned int reverse = ReverseEndian ? 1 : 0;
+      const unsigned int bigend = BigEndianCPU ? 1 : 0;
+      uword64 memval;
+      unsigned int byte;
+
+      paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+      LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
+                 isREAL);
+      byte = (vaddr & mask) ^ (bigend << 2);
+      return EXTEND32 (memval >> (8 * byte));
     }
 
   return 0;

diff --git a/sim/mips/micromips.igen b/sim/mips/micromips.igen
index f24220e6ce974fe3547aa201eebf1f8aaad55432..d444f6dcd96f5daaef3010ff4f9bc1aebf02243e 100644 (file)
--- a/sim/mips/micromips.igen
+++ b/sim/mips/micromips.igen
@@ -845,11 +845,8 @@
   address_word base = GPR[BASE];
   address_word offset = EXTEND12 (IMMEDIATE);
   address_word vaddr = loadstore_ea (SD_, base, offset);
-  address_word paddr;
-  int uncached;
-  if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-                         isTARGET, isREAL))
-    CacheOp (OP, vaddr, paddr, instruction_0);
+  address_word paddr = vaddr;
+  CacheOp (OP, vaddr, paddr, instruction_0);
 }
 
 

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 2862eeb02ea2812d1bbf24e5334e503998cb640a..53370bf3dcf67d5dcc32746b2db41a21b5c7213e 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -782,8 +782,7 @@
   address_word offset = EXTEND16 (insn_offset);
     {
       address_word vaddr = loadstore_ea (SD_, base, offset);
-      address_word paddr;
-      int uncached;
+      address_word paddr = vaddr;
       if ((vaddr & 3) != 0)
        {
          SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
@@ -791,23 +790,19 @@
        }
       else
        {
-         if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-                                 isTARGET, isREAL))
-           {
-             unsigned64 memval = 0;
-             unsigned64 memval1 = 0;
-             unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-             unsigned int shift = 2;
-             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
-             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
-             unsigned int byte;
-             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
-             LoadMemory (&memval, &memval1, uncached, AccessLength_WORD, paddr,
-                        vaddr, isDATA, isREAL);
-             byte = ((vaddr & mask) ^ (bigend << shift));
-             GPR[rt] = EXTEND32 (memval >> (8 * byte));
-             LLBIT = 1;
-           }
+         unsigned64 memval = 0;
+         unsigned64 memval1 = 0;
+         unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+         unsigned int shift = 2;
+         unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
+         unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
+         unsigned int byte;
+         paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
+         LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
+                     isDATA, isREAL);
+         byte = ((vaddr & mask) ^ (bigend << shift));
+         GPR[rt] = EXTEND32 (memval >> (8 * byte));
+         LLBIT = 1;
        }
     }
 }
@@ -818,8 +813,8 @@
   address_word offset = EXTEND16 (roffset);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
+    address_word paddr = vaddr;
+
     if ((vaddr & 7) != 0)
       {
        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
@@ -827,16 +822,12 @@
       }
     else
       {
-       if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-                              isTARGET, isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           LoadMemory (&memval, &memval1, uncached, AccessLength_DOUBLEWORD,
-                       paddr, vaddr, isDATA, isREAL);
-           GPR[rt] = memval;
-           LLBIT = 1;
-         }
+       unsigned64 memval = 0;
+       unsigned64 memval1 = 0;
+       LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
+                   isDATA, isREAL);
+       GPR[rt] = memval;
+       LLBIT = 1;
       }
   }
 }
@@ -1084,13 +1075,8 @@
   address_word offset = EXTEND16 (insn_offset);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    {
-      if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
-                             isTARGET, isREAL))
-       Prefetch (uncached, paddr, vaddr, isDATA, hint);
-    }
+    address_word paddr = vaddr;
+    /* Prefetch (paddr, vaddr, isDATA, hint); */
   }
 }
 
@@ -1101,8 +1087,8 @@
   address_word offset = EXTEND16 (offsetarg);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
+    address_word paddr = vaddr;
+
     if ((vaddr & 3) != 0)
       {
        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
@@ -1110,27 +1096,21 @@
       }
     else
       {
-       if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-                               isTARGET, isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-           address_word reverseendian =
-             (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
-           address_word bigendiancpu =
-             (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-           byte = ((vaddr & mask) ^ bigendiancpu);
-           memval = ((unsigned64) GPR[rt] << (8 * byte));
-           if (LLBIT)
-             {
-               StoreMemory (uncached, AccessLength_WORD, memval, memval1,
-                            paddr, vaddr, isREAL);
-             }
-           GPR[rt] = LLBIT;
-         }
+       unsigned64 memval = 0;
+       unsigned64 memval1 = 0;
+       unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+       address_word reverseendian =
+         (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+       address_word bigendiancpu =
+         (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+       unsigned int byte;
+       paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+       byte = ((vaddr & mask) ^ bigendiancpu);
+       memval = ((unsigned64) GPR[rt] << (8 * byte));
+       if (LLBIT)
+         StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
+                       isREAL);
+       GPR[rt] = LLBIT;
       }
   }
 }
@@ -1141,8 +1121,8 @@
   address_word offset = EXTEND16 (roffset);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
+    address_word paddr = vaddr;
+
     if ((vaddr & 7) != 0)
       {
        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
@@ -1150,19 +1130,13 @@
       }
     else
       {
-       if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-                               isTARGET, isREAL))
-         {
-           unsigned64 memval = 0;
-           unsigned64 memval1 = 0;
-           memval = GPR[rt];
-           if (LLBIT)
-             {
-               StoreMemory (uncached, AccessLength_DOUBLEWORD, memval, memval1,
-                            paddr, vaddr, isREAL);
-             }
-           GPR[rt] = LLBIT;
-         }
+       unsigned64 memval = 0;
+       unsigned64 memval1 = 0;
+       memval = GPR[rt];
+       if (LLBIT)
+         StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
+                      isREAL);
+       GPR[rt] = LLBIT;
       }
   }
 }
@@ -1649,11 +1623,8 @@
   address_word index = GPR[rindex];
   {
     address_word vaddr = loadstore_ea (SD_, base, index);
-    address_word paddr;
-    int uncached;
-    if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
-                           isREAL))
-      Prefetch (uncached, paddr, vaddr, isDATA, hint);
+    address_word paddr = vaddr;
+    /* Prefetch (paddr, vaddr, isDATA, hint); */
   }
 }
 
@@ -1716,8 +1687,8 @@
   check_fpu (SD_);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
+    address_word paddr = vaddr;
+
     if ((vaddr & 3) != 0)
       {
        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
@@ -1725,23 +1696,18 @@
       }
     else
       {
-       if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-                               isTARGET, isREAL))
-         {
-           uword64 memval = 0;
-           uword64 memval1 = 0;
-           uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-           address_word reverseendian =
-             (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
-           address_word bigendiancpu =
-             (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
-           unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-           byte = ((vaddr & mask) ^ bigendiancpu);
-           memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
-           StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
-                        vaddr, isREAL);
-         }
+       uword64 memval = 0;
+       uword64 memval1 = 0;
+       uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+       address_word reverseendian =
+         (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+       address_word bigendiancpu =
+         (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+       unsigned int byte;
+       paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+       byte = ((vaddr & mask) ^ bigendiancpu);
+       memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
+       StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
       }
   }
 }
@@ -1754,8 +1720,8 @@
   check_u64 (SD_, instruction_0);
     {
       address_word vaddr = loadstore_ea (SD_, base, index);
-      address_word paddr;
-      int uncached;
+      address_word paddr = vaddr;
+
       if ((vaddr & 3) != 0)
        {
          SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
@@ -1763,23 +1729,19 @@
        }
       else
        {
-         if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
-                                isTARGET, isREAL))
-           {
-             unsigned64 memval = 0;
-             unsigned64 memval1 = 0;
-             unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
-             address_word reverseendian =
-               (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
-             address_word bigendiancpu =
-               (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
-             unsigned int byte;
-             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-             byte = ((vaddr & mask) ^ bigendiancpu);
-             memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
-             StoreMemory (uncached, AccessLength_WORD, memval, memval1, paddr,
-                          vaddr, isREAL);
-           }
+         unsigned64 memval = 0;
+         unsigned64 memval1 = 0;
+         unsigned64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+         address_word reverseendian =
+           (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
+         address_word bigendiancpu =
+           (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
+         unsigned int byte;
+         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+         byte = ((vaddr & mask) ^ bigendiancpu);
+         memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
+         StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
+                      isREAL);
        }
   }
 }
@@ -3163,18 +3125,16 @@
   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
   unsigned int byte;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
 
-  vaddr = loadstore_ea (SD_, base, offset);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   if ((vaddr & access) != 0)
     {
       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
     }
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
+  LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
   byte = ((vaddr & mask) ^ bigendiancpu);
   return (memval >> (8 * byte));
 }
@@ -3187,7 +3147,6 @@
   unsigned int byte;
   unsigned int word;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
   int nr_lhs_bits;
@@ -3195,8 +3154,7 @@
   unsigned_word lhs_mask;
   unsigned_word temp;
 
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
@@ -3213,7 +3171,7 @@
           (long) ((unsigned64) paddr >> 32), (long) paddr,
           word, byte, nr_lhs_bits, nr_rhs_bits); */
 
-  LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+  LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
   if (word == 0)
     {
       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
@@ -3242,19 +3200,17 @@
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
 
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem != 0)
     paddr = paddr & ~access;
   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
-  LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
+  LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
      (long) paddr, byte, (long) paddr, (long) memval); */
   {
@@ -4043,20 +3999,18 @@
   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
   unsigned int byte;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
 
-  vaddr = loadstore_ea (SD_, base, offset);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   if ((vaddr & access) != 0)
     {
       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
     }
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
   byte = ((vaddr & mask) ^ bigendiancpu);
   memval = (word << (8 * byte));
-  StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
+  StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
 }
 
 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
@@ -4067,14 +4021,12 @@
   unsigned int byte;
   unsigned int word;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
   int nr_lhs_bits;
   int nr_rhs_bits;
 
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
@@ -4101,7 +4053,7 @@
   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
           (long) ((unsigned64) rt >> 32), (long) rt,
           (long) ((unsigned64) memval >> 32), (long) memval); */
-  StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
+  StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
 }
 
 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
@@ -4111,18 +4063,16 @@
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   address_word vaddr;
 
-  vaddr = loadstore_ea (SD_, base, offset);
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem != 0)
     paddr &= ~access;
   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
   memval = (rt << (byte * 8));
-  StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
+  StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
 }
 
 
@@ -5118,24 +5068,20 @@
   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
   address_word vaddr;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
   unsigned64 v;
 
-  vaddr = loadstore_ea (SD_, base, offset);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
     {
       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
                       AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
                       sim_core_unaligned_signal);
     }
-  AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
-                     isREAL);
-  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
-             isDATA, isREAL);
+  LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
   v = (unsigned64)memval;
-  LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
-             isDATA, isREAL);
+  LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
+             isREAL);
   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
 }
 
@@ -5156,24 +5102,19 @@
   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
   address_word vaddr;
   address_word paddr;
-  int uncached;
   unsigned64 memval;
 
-  vaddr = loadstore_ea (SD_, base, offset);
+  paddr = vaddr = loadstore_ea (SD_, base, offset);
   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
     {
       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
                       AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
                       sim_core_unaligned_signal);
     }
-  AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
-                     isREAL);
   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
-  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
-              isREAL);
+  StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
-  StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
-              isREAL);
+  StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
 }
 
 
@@ -6379,10 +6320,8 @@
   address_word offset = EXTEND16 (OFFSET);
   {
     address_word vaddr = loadstore_ea (SD_, base, offset);
-    address_word paddr;
-    int uncached;
-    if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
-      CacheOp(OP,vaddr,paddr,instruction_0);
+    address_word paddr = vaddr;
+    CacheOp(OP, vaddr, paddr, instruction_0);
   }
 }
 

diff --git a/sim/mips/sim-main.c b/sim/mips/sim-main.c
index 916769e7c1f94bc19e73bbdd9492e0327b6acce1..d61ce61fc888d6a5ae2b08aec9c033ad2fbf0935 100644 (file)
--- a/sim/mips/sim-main.c
+++ b/sim/mips/sim-main.c
@@ -28,81 +28,6 @@
 /*---------------------------------------------------------------------------*/
 
 
-/* Description from page A-22 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Translate a virtual address to a physical address and cache
-   coherence algorithm describing the mechanism used to resolve the
-   memory reference. Given the virtual address vAddr, and whether the
-   reference is to Instructions ot Data (IorD), find the corresponding
-   physical address (pAddr) and the cache coherence algorithm (CCA)
-   used to resolve the reference. If the virtual address is in one of
-   the unmapped address spaces the physical address and the CCA are
-   determined directly by the virtual address. If the virtual address
-   is in one of the mapped address spaces then the TLB is used to
-   determine the physical address and access type; if the required
-   translation is not present in the TLB or the desired access is not
-   permitted the function fails and an exception is taken.
-
-   NOTE: Normally (RAW == 0), when address translation fails, this
-   function raises an exception and does not return. */
-
-INLINE_SIM_MAIN
-(int)
-address_translation (SIM_DESC sd,
-                    sim_cpu * cpu,
-                    address_word cia,
-                    address_word vAddr,
-                    int IorD,
-                    int LorS,
-                    address_word * pAddr,
-                    int *CCA,
-                    int raw)
-{
-  int res = -1;                        /* TRUE : Assume good return */
-
-#ifdef DEBUG
-  sim_io_printf (sd, "AddressTranslation(0x%s,%s,%s,...);\n", pr_addr (vAddr), (IorD ? "isDATA" : "isINSTRUCTION"), (LorS ? "iSTORE" : "isLOAD"));
-#endif
-
-  /* Check that the address is valid for this memory model */
-
-  /* For a simple (flat) memory model, we simply pass virtual
-     addressess through (mostly) unchanged. */
-  vAddr &= 0xFFFFFFFF;
-
-  *pAddr = vAddr;              /* default for isTARGET */
-  *CCA = Uncached;             /* not used for isHOST */
-
-  return (res);
-}
-
-
-
-/* Description from page A-23 of the "MIPS IV Instruction Set" manual
-   (revision 3.1) */
-/* Prefetch data from memory. Prefetch is an advisory instruction for
-   which an implementation specific action is taken. The action taken
-   may increase performance, but must not change the meaning of the
-   program, or alter architecturally-visible state. */
-
-INLINE_SIM_MAIN (void)
-prefetch (SIM_DESC sd,
-         sim_cpu *cpu,
-         address_word cia,
-         int CCA,
-         address_word pAddr,
-         address_word vAddr,
-         int DATA,
-         int hint)
-{
-#ifdef DEBUG
-  sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
-#endif /* DEBUG */
-
-  /* For our simple memory model we do nothing */
-  return;
-}
-
 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
    (revision 3.1) */
 /* Load a value from memory. Use the cache and main memory as
@@ -337,15 +262,13 @@ ifetch32 (SIM_DESC SD,
   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
   unsigned int byte;
-  address_word paddr;
-  int uncached;
+  address_word paddr = vaddr;
   unsigned64 memval;
 
   if ((vaddr & access) != 0)
     SignalExceptionInstructionFetch ();
-  AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
+  LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
   byte = ((vaddr & mask) ^ bigendiancpu);
   return (memval >> (8 * byte));
 }
@@ -363,15 +286,13 @@ ifetch16 (SIM_DESC SD,
   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
   unsigned int byte;
-  address_word paddr;
-  int uncached;
+  address_word paddr = vaddr;
   unsigned64 memval;
 
   if ((vaddr & access) != 0)
     SignalExceptionInstructionFetch ();
-  AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
-  LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isINSTRUCTION, isREAL);
+  LoadMemory (&memval, NULL, access, paddr, vaddr, isINSTRUCTION, isREAL);
   byte = ((vaddr & mask) ^ bigendiancpu);
   return (memval >> (8 * byte));
 }

diff --git a/sim/mips/sim-main.h b/sim/mips/sim-main.h
index 88909e58f20a86b7d04ed23b66ea0b8aa1a1885d..c603df4cc0f076a15abf7ab3a973d17ca9d91774 100644 (file)
--- a/sim/mips/sim-main.h
+++ b/sim/mips/sim-main.h
@@ -908,12 +908,6 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 /* The following are generic to all versions of the MIPS architecture
    to date: */
 
-/* Memory Access Types (for CCA): */
-#define Uncached                (0)
-#define CachedNoncoherent       (1)
-#define CachedCoherent          (2)
-#define Cached                  (3)
-
 #define isINSTRUCTION   (1 == 0) /* FALSE */
 #define isDATA          (1 == 1) /* TRUE */
 #define isLOAD          (1 == 0) /* FALSE */
@@ -942,17 +936,13 @@ unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 
 
-INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
-#define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
-address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
-
 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
-#define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
-load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
+#define LoadMemory(memvalp,memval1p,AccessLength,pAddr,vAddr,IorD,raw) \
+load_memory (SD, CPU, cia, memvalp, memval1p, 0, AccessLength, pAddr, vAddr, IorD)
 
 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
-#define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
-store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
+#define StoreMemory(AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
+store_memory (SD, CPU, cia, 0, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 
 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
 #define CacheOp(op,pAddr,vAddr,instruction) \
@@ -962,10 +952,6 @@ INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word c
 #define SyncOperation(stype) \
 sync_operation (SD, CPU, cia, (stype))
 
-INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
-#define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
-prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
-
 void unpredictable_action (sim_cpu *cpu, address_word cia);
 #define NotWordValue(val)      not_word_value (SD_, (val))
 #define Unpredictable()                unpredictable (SD_)