soc/integration: use AXILiteConverter (dummy implementation) in add_adapter()

diff --git a/litex/soc/integration/soc.py b/litex/soc/integration/soc.py
index 28ee0cc220fd9c6f53e8b53fda8cbf3bb641544f..d52402c956aaa083f7fe67f9872d86c9f3f7f2c7 100644 (file)
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@@ -281,35 +281,45 @@ class SoCBusHandler(Module):
     def add_adapter(self, name, interface, direction="m2s"):
         assert direction in ["m2s", "s2m"]
 
-        if isinstance(interface, axi.AXILiteInterface):
-            self.logger.info("{} Bus {} from {} to {}.".format(
-                colorer(name),
-                colorer("converted", color="cyan"),
-                colorer("AXILite"),
-                colorer("Wishbone")))
-            new_interface = wishbone.Interface(data_width=interface.data_width)
-            if direction == "m2s":
-                converter = axi.AXILite2Wishbone(axi_lite=interface, wishbone=new_interface)
-            elif direction == "s2m":
-                converter = axi.Wishbone2AXILite(wishbone=new_interface, axi_lite=interface)
-            self.submodules += converter
-            interface = new_interface
-
-        if interface.data_width != self.data_width:
-            self.logger.info("{} Bus {} from {}-bit to {}-bit.".format(
-                colorer(name),
-                colorer("converted", color="cyan"),
-                colorer(interface.data_width),
-                colorer(self.data_width)))
+        if isinstance(interface, wishbone.Interface):
             new_interface = wishbone.Interface(data_width=self.data_width)
             if direction == "m2s":
                 converter = wishbone.Converter(master=interface, slave=new_interface)
             if direction == "s2m":
                 converter = wishbone.Converter(master=new_interface, slave=interface)
             self.submodules += converter
-            return new_interface
+        elif isinstance(interface, axi.AXILiteInterface):
+            # Data width conversion
+            intermediate = axi.AXILiteInterface(data_width=self.data_width)
+            if direction == "m2s":
+                converter = axi.AXILiteConverter(master=interface, slave=intermediate)
+            if direction == "s2m":
+                converter = axi.AXILiteConverter(master=intermediate, slave=interface)
+            self.submodules += converter
+            # Bus type conversion
+            new_interface = wishbone.Interface(data_width=self.data_width)
+            if direction == "m2s":
+                converter = axi.AXILite2Wishbone(axi_lite=intermediate, wishbone=new_interface)
+            elif direction == "s2m":
+                converter = axi.Wishbone2AXILite(wishbone=new_interface, axi_lite=intermediate)
+            self.submodules += converter
         else:
-            return interface
+            raise TypeError(interface)
+
+        fmt = "{name} Bus {converted} from {frombus} {frombits}-bit to {tobus} {tobits}-bit."
+        frombus  = "Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"
+        tobus    = "Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"
+        frombits = interface.data_width
+        tobits   = new_interface.data_width
+        if frombus != tobus or frombits != tobits:
+            self.logger.info(fmt.format(
+                name      = colorer(name),
+                converted = colorer("converted", color="cyan"),
+                frombus   = colorer("Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"),
+                frombits  = colorer(interface.data_width),
+                tobus     = colorer("Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"),
+                tobits    = colorer(new_interface.data_width)))
+        return new_interface
 
     def add_master(self, name=None, master=None):
         if name is None:

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index cb9c9ad856008f8f3c6371a0a22daaadcc66a73c..02002a58ee9c01913497d7ac1e8ccfb0e919a5f1 100644 (file)
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -676,3 +676,22 @@ class AXILiteSRAM(Module):
                                        port_we=port.we if not read_only else None)
         self.submodules.fsm = fsm
         self.comb += comb
+
+# AXILite Data Width Converter ---------------------------------------------------------------------
+
+class AXILiteConverter(Module):
+    """AXILite data width converter"""
+    def __init__(self, master, slave):
+        self.master = master
+        self.slave = slave
+
+        # # #
+
+        dw_from = len(master.r.data)
+        dw_to = len(slave.r.data)
+        if dw_from > dw_to:
+            raise NotImplementedError
+        elif dw_from < dw_to:
+            raise NotImplementedError
+        else:
+            self.comb += master.connect(slave)