update conversation

diff --git a/3d_gpu/microarchitecture.mdwn b/3d_gpu/microarchitecture.mdwn
index 80796b63545c669bdd41096b0759e35e62b97ad5..f188ec1cf8c13c51fda9441662bf48ba77de794e 100644 (file)
--- a/3d_gpu/microarchitecture.mdwn
+++ b/3d_gpu/microarchitecture.mdwn
@@ -364,35 +364,35 @@ scoreboards are not just scoreboards, they are dependency matrices,
 and there are several of them:
 
 * one for LOAD/STORE-to-LOAD/STORE:
-    1. most recent LOADs prevent later STOREs
-    2. most recent STOREs prevent later LOADs.
+    - most recent LOADs prevent later STOREs
+    - most recent STOREs prevent later LOADs.
 * one for Function-Unit to Function-Unit.
-    3. it expresses both RAW and WAW hazards through "Go_Write"
+    - it expresses both RAW and WAW hazards through "Go_Write"
      and "Go_Read" signals, which are stopped from proceeding by
      dependent 1-bit CAM latches
-    4. exceptions may ALSO be made "precise" by holding a "Write prevention"
+    - exceptions may ALSO be made "precise" by holding a "Write prevention"
      signal.  only when the Function Unit knows that an exception is
      not going to occur (memory has been fetched, for example), does
      it release the signal
-    5. speculative branch execution likewise may hold a "Write prevention",
+    - speculative branch execution likewise may hold a "Write prevention",
        however it also needs a "Go die" signal, to clear out the
        incorrectly-taken branch.
-    6. LOADs/STOREs *also* must be considered as "Functional Units" and thus
+    - LOADs/STOREs *also* must be considered as "Functional Units" and thus
        must also have corresponding entries (plural) in the FU-to-FU Matrix
-    7. it is permitted for ALUs to *BEGIN* execution (read operands are
+    - it is permitted for ALUs to *BEGIN* execution (read operands are
        valid) without being permitted to *COMMIT*.  thus, each FU must
        store (buffer) results, until such time as a "commit" signal is
        received
-    8. we may need to express an inter-dependence on the instruction order
+    - we may need to express an inter-dependence on the instruction order
        (raising the WAW hazard line to do so) as a way to preserve execution
        order.  only the oldest instructions will have this flag dropped,
        permitting execution that has *begun* to also reach "commit" phase.
 * one for Function-Unit to Registers.
-    1. it expresses the read and write requirements: the source
+    - it expresses the read and write requirements: the source
       and destination registers on which the operation depends.  source
       registers are marked "need read", dest registers marked
       "need write".
-    2. by having *more than one* Functional Unit matrix row per ALU
+    - by having *more than one* Functional Unit matrix row per ALU
       it becomes possible to effectively achieve "Reservation Stations"
       orthogonality with the Tomasulo Algorithm.  the FU row must, like
       RS's, take and store a copy of the src register values.