/*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
#include "mem/packet_access.hh"
VGic::VGic(const Params *p)
- : PioDevice(p), platform(p->platform), gic(p->gic), vcpuAddr(p->vcpu_addr),
- hvAddr(p->hv_addr), pioDelay(p->pio_delay),
- maintInt(p->ppint)
+ : PioDevice(p), gicvIIDR(p->gicv_iidr), platform(p->platform),
+ gic(p->gic), vcpuAddr(p->vcpu_addr), hvAddr(p->hv_addr),
+ pioDelay(p->pio_delay), maintInt(p->ppint)
{
for (int x = 0; x < VGIC_CPU_MAX; x++) {
postVIntEvent[x] = new EventFunctionWrapper(
lr->VirtualID, lr->CpuID, i, lr->EOI);
}
} break;
+ case GICV_IIDR:
+ pkt->setLE<uint32_t>(gicvIIDR);
+ break;
default:
panic("VGIC VCPU read of bad address %#x\n", daddr);
}
/*
- * Copyright (c) 2013 ARM Limited
+ * Copyright (c) 2013,2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
static const uint32_t LR_PENDING = 1;
static const uint32_t LR_ACTIVE = 2;
+ const uint32_t gicvIIDR;
/** Post interrupt to CPU */
void processPostVIntEvent(uint32_t cpu);