+cd tests/aiger && bash run-test.sh $(ABCOPT)
+cd tests/arch && bash run-test.sh
+cd tests/ice40 && bash run-test.sh $(SEEDOPT)
+ +cd tests/anlogic && bash run-test.sh $(SEEDOPT)
@echo ""
@echo " Passed \"make test\"."
@echo ""
--- /dev/null
+*.log
+/run-test.mk
++*_synth.v
++*_testbench
--- /dev/null
+module top
+(
+ input [3:0] x,
+ input [3:0] y,
+
+ output [3:0] A,
+ output [3:0] B
+ );
+
+assign A = x + y;
+assign B = x - y;
+
+endmodule
--- /dev/null
+read_verilog add_sub.v
+hierarchy -top top
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 10 t:AL_MAP_ADDER
+select -assert-count 4 t:AL_MAP_LUT1
+select -assert-none t:AL_MAP_LUT1 t:AL_MAP_ADDER %% t:* %D
+
--- /dev/null
+module top (
+ input clock,
+ input [31:0] dinA, dinB,
+ input [2:0] opcode,
+ output reg [31:0] dout
+);
+ always @(posedge clock) begin
+ case (opcode)
+ 0: dout <= dinA + dinB;
+ 1: dout <= dinA - dinB;
+ 2: dout <= dinA >> dinB;
+ 3: dout <= $signed(dinA) >>> dinB;
+ 4: dout <= dinA << dinB;
+ 5: dout <= dinA & dinB;
+ 6: dout <= dinA | dinB;
+ 7: dout <= dinA ^ dinB;
+ endcase
+ end
+endmodule
--- /dev/null
+read_verilog alu.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 66 t:AL_MAP_ADDER
+select -assert-count 32 t:AL_MAP_LUT1
+select -assert-count 23 t:AL_MAP_LUT2
+select -assert-count 61 t:AL_MAP_LUT3
+select -assert-count 209 t:AL_MAP_LUT4
+select -assert-count 100 t:AL_MAP_LUT5
+select -assert-count 79 t:AL_MAP_LUT6
+select -assert-count 32 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_ADDER t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
--- /dev/null
+module top (\r
+out,\r
+clk,\r
+reset\r
+);\r
+ output [7:0] out;\r
+ input clk, reset;\r
+ reg [7:0] out;\r
+\r
+ always @(posedge clk, posedge reset)\r
+ if (reset) begin\r
+ out <= 8'b0 ;\r
+ end else\r
+ out <= out + 1;\r
+\r
+\r
+endmodule\r
--- /dev/null
+read_verilog counter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 9 t:AL_MAP_ADDER
+select -assert-count 8 t:AL_MAP_SEQ
+select -assert-none t:SB_CARRY t:AL_MAP_SEQ t:AL_MAP_ADDER %% t:* %D
--- /dev/null
+module dff
+ ( input d, clk, output reg q );
+ always @( posedge clk )
+ q <= d;
+endmodule
+
+module dffe
+ ( input d, clk, en, output reg q );
+ initial begin
+ q = 0;
+ end
+ always @( posedge clk )
+ if ( en )
+ q <= d;
+endmodule
+
+module top (
+input clk,
+input en,
+input a,
+output b,b1,
+);
+
+dff u_dff (
+ .clk (clk ),
+ .d (a ),
+ .q (b )
+ );
+
+dffe u_ndffe (
+ .clk (clk ),
+ .en (en),
+ .d (a ),
+ .q (b1 )
+ );
+
+endmodule
--- /dev/null
+read_verilog dffs.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT3
+select -assert-count 2 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_SEQ %% t:* %D
--- /dev/null
+ module fsm (\r
+ clock,\r
+ reset,\r
+ req_0,\r
+ req_1,\r
+ gnt_0,\r
+ gnt_1\r
+ );\r
+ input clock,reset,req_0,req_1;\r
+ output gnt_0,gnt_1;\r
+ wire clock,reset,req_0,req_1;\r
+ reg gnt_0,gnt_1;\r
+\r
+ parameter SIZE = 3 ;\r
+ parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100,GNT2 = 3'b101 ;\r
+\r
+ reg [SIZE-1:0] state;\r
+ reg [SIZE-1:0] next_state;\r
+\r
+ always @ (posedge clock)\r
+ begin : FSM\r
+ if (reset == 1'b1) begin\r
+ state <= #1 IDLE;\r
+ gnt_0 <= 0;\r
+ gnt_1 <= 0;\r
+ end else\r
+ case(state)\r
+ IDLE : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT0;\r
+ gnt_0 <= 1;\r
+ end else if (req_1 == 1'b1) begin\r
+ gnt_1 <= 1;\r
+ state <= #1 GNT0;\r
+ end else begin\r
+ state <= #1 IDLE;\r
+ end\r
+ GNT0 : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT0;\r
+ end else begin\r
+ gnt_0 <= 0;\r
+ state <= #1 IDLE;\r
+ end\r
+ GNT1 : if (req_1 == 1'b1) begin\r
+ state <= #1 GNT2;\r
+ gnt_1 <= req_0;\r
+ end\r
+ GNT2 : if (req_0 == 1'b1) begin\r
+ state <= #1 GNT1;\r
+ gnt_1 <= req_1;\r
+ end\r
+ default : state <= #1 IDLE;\r
+ endcase\r
+ end\r
+\r
+ endmodule\r
+\r
+ module top (\r
+input clk,\r
+input rst,\r
+input a,\r
+input b,\r
+output g0,\r
+output g1\r
+);\r
+\r
+fsm u_fsm ( .clock(clk),\r
+ .reset(rst),\r
+ .req_0(a),\r
+ .req_1(b),\r
+ .gnt_0(g0),\r
+ .gnt_1(g1));\r
+\r
+endmodule\r
--- /dev/null
+read_verilog fsm.v
+hierarchy -top top
+proc
+flatten
+#ERROR: Found 4 unproven $equiv cells in 'equiv_status -assert'.
+#equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+equiv_opt -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:AL_MAP_LUT2
+select -assert-count 5 t:AL_MAP_LUT5
+select -assert-count 1 t:AL_MAP_LUT6
+select -assert-count 6 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT5 t:AL_MAP_LUT6 t:AL_MAP_SEQ %% t:* %D
--- /dev/null
+module latchp
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( en )
+ q <= d;
+endmodule
+
+module latchn
+ ( input d, clk, en, output reg q );
+ always @*
+ if ( !en )
+ q <= d;
+endmodule
+
+module latchsr
+ ( input d, clk, en, clr, pre, output reg q );
+ always @*
+ if ( clr )
+ q <= 1'b0;
+ else if ( pre )
+ q <= 1'b1;
+ else if ( en )
+ q <= d;
+endmodule
+
+
+module top (
+input clk,
+input clr,
+input pre,
+input a,
+output b,b1,b2
+);
+
+
+latchp u_latchp (
+ .en (clk ),
+ .d (a ),
+ .q (b )
+ );
+
+
+latchn u_latchn (
+ .en (clk ),
+ .d (a ),
+ .q (b1 )
+ );
+
+
+latchsr u_latchsr (
+ .en (clk ),
+ .clr (clr),
+ .pre (pre),
+ .d (a ),
+ .q (b2 )
+ );
+
+endmodule
--- /dev/null
+read_verilog latches.v
+design -save read
+
+proc
+async2sync # converts latches to a 'sync' variant clocked by a 'super'-clock
+flatten
+synth_anlogic
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+
+design -load read
+synth_anlogic
+cd top
+select -assert-count 2 t:AL_MAP_LUT3
+select -assert-count 1 t:AL_MAP_LUT5
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT5 %% t:* %D
--- /dev/null
+module top
+(
+ input [7:0] data_a,
+ input [6:1] addr_a,
+ input we_a, clk,
+ output reg [7:0] q_a
+);
+ // Declare the RAM variable
+ reg [7:0] ram[63:0];
+
+ // Port A
+ always @ (posedge clk)
+ begin
+ if (we_a)
+ begin
+ ram[addr_a] <= data_a;
+ q_a <= data_a;
+ end
+ q_a <= ram[addr_a];
+ end
+endmodule
--- /dev/null
+read_verilog memory.v
+hierarchy -top top
+proc
+memory -nomap
+equiv_opt -run :prove -map +/anlogic/cells_sim.v synth_anlogic
+memory
+opt -full
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+#ERROR: Failed to import cell gate.mem.0.0.0 (type EG_LOGIC_DRAM16X4) to SAT database.
+#sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter
+
+design -load postopt
+cd top
+
+select -assert-count 8 t:AL_MAP_LUT2
+select -assert-count 8 t:AL_MAP_LUT4
+select -assert-count 8 t:AL_MAP_LUT5
+select -assert-count 36 t:AL_MAP_SEQ
+select -assert-count 8 t:EG_LOGIC_DRAM16X4 #Why not AL_LOGIC_BRAM?
+select -assert-none t:AL_MAP_LUT2 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_SEQ t:EG_LOGIC_DRAM16X4 %% t:* %D
--- /dev/null
+module mux2 (S,A,B,Y);
+ input S;
+ input A,B;
+ output reg Y;
+
+ always @(*)
+ Y = (S)? B : A;
+endmodule
+
+module mux4 ( S, D, Y );
+
+input[1:0] S;
+input[3:0] D;
+output Y;
+
+reg Y;
+wire[1:0] S;
+wire[3:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ endcase
+end
+
+endmodule
+
+module mux8 ( S, D, Y );
+
+input[2:0] S;
+input[7:0] D;
+output Y;
+
+reg Y;
+wire[2:0] S;
+wire[7:0] D;
+
+always @*
+begin
+ case( S )
+ 0 : Y = D[0];
+ 1 : Y = D[1];
+ 2 : Y = D[2];
+ 3 : Y = D[3];
+ 4 : Y = D[4];
+ 5 : Y = D[5];
+ 6 : Y = D[6];
+ 7 : Y = D[7];
+ endcase
+end
+
+endmodule
+
+module mux16 (D, S, Y);
+ input [15:0] D;
+ input [3:0] S;
+ output Y;
+
+assign Y = D[S];
+
+endmodule
+
+
+module top (
+input [3:0] S,
+input [15:0] D,
+output M2,M4,M8,M16
+);
+
+mux2 u_mux2 (
+ .S (S[0]),
+ .A (D[0]),
+ .B (D[1]),
+ .Y (M2)
+ );
+
+
+mux4 u_mux4 (
+ .S (S[1:0]),
+ .D (D[3:0]),
+ .Y (M4)
+ );
+
+mux8 u_mux8 (
+ .S (S[2:0]),
+ .D (D[7:0]),
+ .Y (M8)
+ );
+
+mux16 u_mux16 (
+ .S (S[3:0]),
+ .D (D[15:0]),
+ .Y (M16)
+ );
+
+endmodule
--- /dev/null
+read_verilog mux.v
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+
+select -assert-count 1 t:AL_MAP_LUT3
+select -assert-count 4 t:AL_MAP_LUT4
+select -assert-count 4 t:AL_MAP_LUT5
+select -assert-count 1 t:AL_MAP_LUT6
+select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D
--- /dev/null
+#!/usr/bin/env bash
+set -e
+{
+echo "all::"
+for x in *.ys; do
+ echo "all:: run-$x"
+ echo "run-$x:"
+ echo " @echo 'Running $x..'"
+ echo " @../../yosys -ql ${x%.ys}.log $x -w 'Yosys has only limited support for tri-state logic at the moment.'"
+done
+for s in *.sh; do
+ if [ "$s" != "run-test.sh" ]; then
+ echo "all:: run-$s"
+ echo "run-$s:"
+ echo " @echo 'Running $s..'"
+ echo " @bash $s"
+ fi
+done
+} > run-test.mk
+exec ${MAKE:-make} -f run-test.mk
--- /dev/null
+module top (\r
+out,\r
+clk,\r
+in\r
+);\r
+ output [7:0] out;\r
+ input signed clk, in;\r
+ reg signed [7:0] out = 0;\r
+\r
+ always @(posedge clk)\r
+ begin\r
+`ifndef BUG\r
+ out <= out >> 1;\r
+ out[7] <= in;\r
+`else\r
+\r
+ out <= out << 1;\r
+ out[7] <= in;\r
+`endif\r
+ end\r
+\r
+endmodule\r
--- /dev/null
+read_verilog shifter.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 8 t:AL_MAP_SEQ
+select -assert-none t:AL_MAP_SEQ %% t:* %D
--- /dev/null
+module tristate (en, i, o);
+ input en;
+ input i;
+ output o;
+
+ assign o = en ? i : 1'bz;
+
+endmodule
+
+
+module top (
+input en,
+input a,
+output b
+);
+
+tristate u_tri (
+ .en (en ),
+ .i (a ),
+ .o (b )
+ );
+
+endmodule
--- /dev/null
+read_verilog tribuf.v
+hierarchy -top top
+proc
+flatten
+equiv_opt -assert -map +/anlogic/cells_sim.v -map +/simcells.v synth_anlogic # equivalency check
+design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
+cd top # Constrain all select calls below inside the top module
+select -assert-count 1 t:$_TBUF_
+select -assert-none t:$_TBUF_ %% t:* %D
projects / yosys.git / commitdiff