soc/integration/cpu_interface: improve code legibility

Factor out code appearing in both branches of an if/else.

diff --git a/litex/soc/integration/cpu_interface.py b/litex/soc/integration/cpu_interface.py
index c80dbccd6dd466b0433c0e2653a199ca0db93017..d20f06ebe9fd2e60a70b6f6b0389ae46f50117e3 100644 (file)
--- a/litex/soc/integration/cpu_interface.py
+++ b/litex/soc/integration/cpu_interface.py
@@ -140,12 +140,9 @@ def get_csr_header(regions, constants, with_access_functions=True, with_shadow_b
     for name, origin, busword, obj in regions:
         if not with_shadow_base:
             origin &= (~shadow_base)
-        if isinstance(obj, Memory):
-            r += "\n/* "+name+" */\n"
-            r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"L\n"
-        else:
-            r += "\n/* "+name+" */\n"
-            r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"L\n"
+        r += "\n/* "+name+" */\n"
+        r += "#define CSR_"+name.upper()+"_BASE "+hex(origin)+"L\n"
+        if not isinstance(obj, Memory):
             for csr in obj:
                 nr = (csr.size + busword - 1)//busword
                 r += _get_rw_functions_c(name + "_" + csr.name, origin, nr, busword, isinstance(csr, CSRStatus), with_access_functions)