\tableofcontents
+% Part II
\part{Scalable Vectors for the Power ISA}
\end{appendices}
+% Part III
\part{Scalar Instructions}
+\chapter*{Preamble}{}
+
+As explained in the Simple-V introduction
+these are all intentionally and specifically Scalar instructions.
+They have with almost no exceptions been specifically crafted to
+have a justification for their inclusion in the Power ISA as Scalar
+instructions purely on their own merit.
+
+\begin{itemize}
+ \item The biginteger multiply-and-add instruction is similar
+ to Intel's mulx in that it produces a pair of results.
+ \item Javascript(tm) rounding is present in ARM as fjcvtzs
+ and would save an astounding 35 instructions with 5 branches.
+ \item Whilst there exist CR bit manipulation and copying
+ instructions there are no CR Field maniulation instructions,
+ putting pressure on GPRs if several CR fits need to be analysed.
+\end{itemize}
+
+All of these have nothing to do with Simple-V at all.
+
+That said: by a wonderful coincidence, should they be included, then
+Simple-V's capabilities increase significantly. For example the CRweird
+instructions combined with the bitmanip instructions, alongside
+Vectorised Rc=1 turn CR Fields into
+extremely powerful Predicate masks.
+
+The clean and clear separation between Vectorisation Prefix and Scalar
+Suffix is what makes it possible for both Scalar-only and Scalable-Vectors
+to benefit. It also makes proposal much easier, as there is no
+inter-dependence.
+
+It is however important to note that the rationale for these instructions
+comes from a more general-purpose moderen computing paradigm that is
+outside of IBM's much more focussed and specialist traditional customer
+base. We deeply respect IBM's curator role of the Power ISA of the past 25
+years as much as we appreciate their courage in transferring that role
+to the OpenPOWER Foundation ISA Working Group.
+
\chapter{SV Vector ops}\hypertarget{svux2fvector_ops}{}
\input{tex_out/vector_ops.tex}
\chapter{CR Weird ops}\hypertarget{svux2fcr_int_predication}{}
\input{tex_out/pseudocode_svfixedarith.tex}
\end{appendices}
+% Part IV
\part{Scalar Power ISA pseudocode}
\backmatter % temporary fix for too many appenfices
%\setcounter{chapter}{0}