(no commit message)

diff --git a/openpower/sv/SimpleV_rationale.mdwn b/openpower/sv/SimpleV_rationale.mdwn
index e92228cb1e6daddc0814f324bf979a9c242b650e..f64d893d2fc409f056b9df8b0a8d14da0d8289d7 100644 (file)
--- a/openpower/sv/SimpleV_rationale.mdwn
+++ b/openpower/sv/SimpleV_rationale.mdwn
@@ -400,7 +400,8 @@ ISA, the amount of data processing requested
 and controlled by each instruction is enormous, and leaves the
 Decode and Issue Engines idle, as well as the L1 I-Cache. With
 programs being smaller, chances are higher that they fit into
-L1 Cache, or that the L1 Cache may be made smaller.
+L1 Cache, or that the L1 Cache may be made smaller: either way
+is a considerable O(N^2) power-saving.
 
 Even a Packed SIMD ISA could take limited advantage of a higher
 bang-per-buck for limited specific workloads, as long as the