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diff --git a/openpower/sv/svp64/appendix.mdwn b/openpower/sv/svp64/appendix.mdwn
index bb163869d2a91965a43e0d7b1f65504ed75c2b88..2eed126e8cb9403af2441473fbf10eaaf1906e1f 100644 (file)
--- a/openpower/sv/svp64/appendix.mdwn
+++ b/openpower/sv/svp64/appendix.mdwn
@@ -276,7 +276,7 @@ through the Power ISA WG Process). It would
 be similar to deciding that `add` should be changed from X-Form
 to D-Form.
 
-# Single Predication
+# Single Predication <a name="1p"> </a>
 
 This is a standard mode normally found in Vector ISAs.  every element in every source Vector and in the destination uses the same bit of one single predicate mask.
 
@@ -338,7 +338,7 @@ The following schedule for srcstep and dststep will occur:
 
 Here, both srcstep and dststep remain in lockstep because sz=dz=1
 
-# Twin Predication
+# Twin Predication <a name="2p"> </a>
 
 This is a novel concept that allows predication to be applied to a single
 source and a single dest register.  The following types of traditional