gallium/radeon: set num_banks in the winsys

amdgpu doesn't have to set this, because radeonsi gets it from tile mode
arrays by default.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c
index a7e673a3b1f74ac5bac34d76977e44323c6907df..9a0a30e3a6f36dfb34dfa04d566e0a473cf4b181 100644 (file)
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -772,7 +772,7 @@ evergreen_create_sampler_view_custom(struct pipe_context *ctx,
                if (util_format_get_blocksize(pipe_format) >= 16)
                        non_disp_tiling = 1;
        }
-       nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
+       nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
 
        if (state->target == PIPE_TEXTURE_1D_ARRAY) {
                height = 1;
@@ -1098,7 +1098,7 @@ void evergreen_init_color_surface(struct r600_context *rctx,
                if (util_format_get_blocksize(surf->base.format) >= 16)
                        non_disp_tiling = 1;
        }
-       nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
+       nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
        desc = util_format_description(surf->base.format);
        for (i = 0; i < 4; i++) {
                if (desc->channel[i].type != UTIL_FORMAT_TYPE_VOID) {
@@ -1253,7 +1253,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
        macro_aspect = eg_macro_tile_aspect(macro_aspect);
        bankw = eg_bank_wh(bankw);
        bankh = eg_bank_wh(bankh);
-       nbanks = eg_num_banks(rscreen->b.tiling_info.num_banks);
+       nbanks = eg_num_banks(rscreen->b.info.r600_num_banks);
        offset >>= 8;
 
        surf->db_z_info = S_028040_ARRAY_MODE(array_mode) |
@@ -3467,7 +3467,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
        sub_cmd = EG_DMA_COPY_TILED;
        lbpp = util_logbase2(bpp);
        pitch_tile_max = ((pitch / bpp) / 8) - 1;
-       nbanks = eg_num_banks(rctx->screen->b.tiling_info.num_banks);
+       nbanks = eg_num_banks(rctx->screen->b.info.r600_num_banks);
 
        if (dst_mode == RADEON_SURF_MODE_LINEAR) {
                /* T2L */

diff --git a/src/gallium/drivers/r600/r600_uvd.c b/src/gallium/drivers/r600/r600_uvd.c
index 18d2b69afb076fc604f88f1018fc41ecffd19d9f..0c9283457739bea5576c059e56121991b900736a 100644 (file)
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -160,7 +160,7 @@ static struct pb_buffer* r600_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_
        struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
 
        msg->body.decode.dt_field_mode = buf->base.interlaced;
-       msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.tiling_info.num_banks));
+       msg->body.decode.dt_surf_tile_config |= RUVD_NUM_BANKS(eg_num_banks(rscreen->b.info.r600_num_banks));
 
        ruvd_set_dt_surfaces(msg, &luma->surface, &chroma->surface);
 

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c
index e0c2469747e35cebc70d1a2e59fedabba235ca5c..ec1d882f8c016e4188ea98590cb1b8bc1eb6504e 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -803,17 +803,6 @@ static boolean r600_fence_finish(struct pipe_screen *screen,
 static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
                                  uint32_t tiling_config)
 {
-       switch ((tiling_config & 0x30) >> 4) {
-       case 0:
-               rscreen->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               rscreen->tiling_info.num_banks = 8;
-               break;
-       default:
-               return false;
-
-       }
        switch ((tiling_config & 0xc0) >> 6) {
        case 0:
                rscreen->tiling_info.group_bytes = 256;
@@ -830,20 +819,6 @@ static bool r600_interpret_tiling(struct r600_common_screen *rscreen,
 static bool evergreen_interpret_tiling(struct r600_common_screen *rscreen,
                                       uint32_t tiling_config)
 {
-       switch ((tiling_config & 0xf0) >> 4) {
-       case 0:
-               rscreen->tiling_info.num_banks = 4;
-               break;
-       case 1:
-               rscreen->tiling_info.num_banks = 8;
-               break;
-       case 2:
-               rscreen->tiling_info.num_banks = 16;
-               break;
-       default:
-               return false;
-       }
-
        switch ((tiling_config & 0xf00) >> 8) {
        case 0:
                rscreen->tiling_info.group_bytes = 256;
@@ -981,6 +956,7 @@ bool r600_common_screen_init(struct r600_common_screen *rscreen,
                printf("r600_gb_backend_map = %i\n", rscreen->info.r600_gb_backend_map);
                printf("r600_gb_backend_map_valid = %i\n", rscreen->info.r600_gb_backend_map_valid);
                printf("r600_tiling_config = 0x%x\n", rscreen->info.r600_tiling_config);
+               printf("r600_num_banks = %i\n", rscreen->info.r600_num_banks);
                printf("num_render_backends = %i\n", rscreen->info.num_render_backends);
                printf("num_tile_pipes = %i\n", rscreen->info.num_tile_pipes);
                printf("si_tile_mode_array_valid = %i\n", rscreen->info.si_tile_mode_array_valid);

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h b/src/gallium/drivers/radeon/r600_pipe_common.h
index 0c44bd7de00d8c1fcfb8d74ef5d565e05f6452f7..52c517fb3e48e4097b5b5d5c3b81e6b062087d34 100644 (file)
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -282,7 +282,6 @@ struct r600_surface {
 };
 
 struct r600_tiling_info {
-       unsigned num_banks;
        unsigned group_bytes;
 };
 

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index 25b90558a667877b60b6ef9f9ab048d068041835..b4cca0efcec4a682fb5f9bf20335997bd7124aca 100644 (file)
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -277,6 +277,7 @@ struct radeon_info {
     uint32_t                    r300_num_z_pipes;
     uint32_t                    r600_gb_backend_map; /* R600 harvest config */
     boolean                     r600_gb_backend_map_valid;
+    uint32_t                    r600_num_banks;
     uint32_t                    r600_tiling_config;
     uint32_t                    num_render_backends;
     uint32_t                    num_tile_pipes; /* pipe count from PIPE_CONFIG */

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 580aa7890989f77331cb01c0ac681ddd4d451f20..bf780777b50c021830607bc51b3a3e5d1093f48d 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -97,7 +97,7 @@ uint32_t si_num_banks(struct si_screen *sscreen, struct r600_texture *tex)
        }
 
        /* The old way. */
-       switch (sscreen->b.tiling_info.num_banks) {
+       switch (sscreen->b.info.r600_num_banks) {
        case 2:
                return V_02803C_ADDR_SURF_2_BANK;
        case 4:

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index b97ccfd16797d4a69f9029df861894eda0ceadde..f857a14e0338510ddd24dbf7bd93d0c15e709321 100644 (file)
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -385,6 +385,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
         radeon_get_drm_value(ws->fd, RADEON_INFO_TILING_CONFIG, NULL,
                              &ws->info.r600_tiling_config);
 
+        ws->info.r600_num_banks =
+            ws->info.chip_class >= EVERGREEN ?
+                4 << ((ws->info.r600_tiling_config & 0xf0) >> 4) :
+                4 << ((ws->info.r600_tiling_config & 0x30) >> 4);
+
         if (ws->info.drm_minor >= 11) {
             radeon_get_drm_value(ws->fd, RADEON_INFO_NUM_TILE_PIPES, NULL,
                                  &ws->info.num_tile_pipes);