ISA Spec,
is under severe design pressure as it is insufficient to hold
the full extent of the instruction additions required to create
-a Hybrid 3D CPU-VPU-GPU.
+a Hybrid 3D CPU-VPU-GPU. Akthough the wording of the Power ISA
+Specification leaves open the *possibility* of not needing to
+propose ISA Extensions to the ISA WG, it is clear that EXT022
+is an inappropriate location for a large high-profile Extension
+intended for mass-volume product deployment. Every in-good-faith effort will
+therefore be made to work with the OPF ISA WG to
+submit SVP64 via the External RFC Process.
**Whilst SVP64 is only 5 instructions
the heavy focus on VSX for the past 12 years has left the SFFS Level