added log_header to miter and expose pass, show cell type for exposed ports

diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 2ac7b35f6136117a51cd55e3ab0305caee227eda..831a43aa5094a0abee4adc87f790cdabf8d9c7ba 100644 (file)
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -259,6 +259,8 @@ struct ExposePass : public Pass {
                bool flag_evert_dff = false;
                std::string sep = ".";
 
+               log_header("Executing EXPOSE pass (exposing internal signals as outputs).\n");
+
                size_t argidx;
                for (argidx = 1; argidx < args.size(); argidx++)
                {
@@ -629,7 +631,7 @@ struct ExposePass : public Pass {
                                                                w->port_input = true;
                                                        add_new_wire(module, w);
 
-                                                       log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+                                                       log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
                                                        RTLIL::SigSpec sig;
                                                        if (cell->connections.count(p->name) != 0)
@@ -654,7 +656,7 @@ struct ExposePass : public Pass {
                                                                w->port_input = true;
                                                        add_new_wire(module, w);
 
-                                                       log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name));
+                                                       log("New module port: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(w->name), RTLIL::id2cstr(cell->type));
 
                                                        if (w->port_input)
                                                                module->connections.push_back(RTLIL::SigSig(it.second, w));
@@ -667,7 +669,7 @@ struct ExposePass : public Pass {
                                }
 
                                for (auto &it : delete_cells) {
-                                       log("Removing cell: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it));
+                                       log("Removing cell: %s/%s (%s)\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(it), RTLIL::id2cstr(module->cells.at(it)->type));
                                        delete module->cells.at(it);
                                        module->cells.erase(it);
                                }

diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc
index db12cb57d779fdff7efbbaa73bae14563ee25cc0..6c8e2ff48eb80e288dee57d7538c9ea0c11d8e2b 100644 (file)
--- a/passes/sat/miter.cc
+++ b/passes/sat/miter.cc
@@ -28,6 +28,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
        bool flag_make_outcmp = false;
        bool flag_make_assert = false;
 
+       log_header("Executing MITER pass (creating miter circuit).\n");
+
        size_t argidx;
        for (argidx = 2; argidx < args.size(); argidx++)
        {
@@ -102,6 +104,8 @@ static void create_miter_equiv(struct Pass *that, std::vector<std::string> args,
                log_cmd_error("No matching port in gold module was found for %s!\n", it.second->name.c_str());
        }
 
+       log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name));
+
        RTLIL::Module *miter_module = new RTLIL::Module;
        miter_module->name = miter_name;
        design->modules[miter_name] = miter_module;