--- /dev/null
+TARGET_ISA = 'alpha'
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'alpha'
-FULL_SYSTEM = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MI_example'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MESI_CMP_directory'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_directory'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_CMP_token'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MOESI_hammer'
--- /dev/null
+SS_COMPATIBLE_FP = 1
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'Network_test'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MI_example'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MESI_CMP_directory'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MOESI_CMP_directory'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MOESI_CMP_token'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MOESI_hammer'
+++ /dev/null
-FULL_SYSTEM = 0
-SS_COMPATIBLE_FP = 1
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'Network_test'
--- /dev/null
+TARGET_ISA = 'arm'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'arm'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-FULL_SYSTEM = 1
-PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'arm'
-FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-PROTOCOL = 'MI_example'
--- /dev/null
+TARGET_ISA = 'mips'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'mips'
-FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-PROTOCOL = 'MI_example'
--- /dev/null
+TARGET_ISA = 'power'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'power'
-FULL_SYSTEM = 0
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-PROTOCOL = 'MI_example'
--- /dev/null
+TARGET_ISA = 'sparc'
+CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'sparc'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU'
-FULL_SYSTEM = 1
-PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'sparc'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU'
-FULL_SYSTEM = 0
-PROTOCOL = 'MI_example'
--- /dev/null
+TARGET_ISA = 'x86'
+CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
+PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'x86'
-CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'
-FULL_SYSTEM = 1
-PROTOCOL = 'MI_example'
+++ /dev/null
-TARGET_ISA = 'x86'
-CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
-FULL_SYSTEM = 0
-PROTOCOL = 'MI_example'