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i965: Check for miptree pitch alignment before using intel_miptree_map_movntdqa()
author
Anuj Phogat
<anuj.phogat@gmail.com>
Tue, 5 May 2015 06:10:28 +0000
(23:10 -0700)
committer
Anuj Phogat
<anuj.phogat@gmail.com>
Mon, 15 Jun 2015 16:07:28 +0000
(09:07 -0700)
We have an assert() in intel_miptree_map_movntdqa() which expects
the pitch to be 16 byte aligned.
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
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diff --git
a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 8addcc5010c9697cc819d50b62bdc073b205aeee..593bb9da0d5e9eeb06bdcafc1b9b58c07f94a598 100644
(file)
--- a/
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/
src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@
-2630,7
+2630,9
@@
intel_miptree_map(struct brw_context *brw,
} else if (use_intel_mipree_map_blit(brw, mt, mode, level, slice)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
#if defined(USE_SSE41)
- } else if (!(mode & GL_MAP_WRITE_BIT) && !mt->compressed && cpu_has_sse4_1) {
+ } else if (!(mode & GL_MAP_WRITE_BIT) &&
+ !mt->compressed && cpu_has_sse4_1 &&
+ (mt->pitch % 16 == 0)) {
intel_miptree_map_movntdqa(brw, mt, map, level, slice);
#endif
} else {