fix rpcc

arch/alpha/ev5.cc:
    actually implement the cycle count register
arch/alpha/isa_desc:
    the rpcc instruction really just reads the cycle count
    register

--HG--
extra : convert_revision : a0edec85672377a62b90950efc17b62b375220b1

diff --git a/arch/alpha/ev5.cc b/arch/alpha/ev5.cc
index 96c51a2aaae08d8f7ee9d49f15f3f94fdde3f7b6..551cbdabfda7737430ff1a830edf619da395ee00 100644 (file)
--- a/arch/alpha/ev5.cc
+++ b/arch/alpha/ev5.cc
@@ -237,6 +237,11 @@ ExecContext::readIpr(int idx, Fault &fault)
         retval = ipr[idx];
         break;
 
+      case AlphaISA::IPR_CC:
+        retval |= ipr[idx] & ULL(0xffffffff00000000);
+        retval |= curTick  & ULL(0x00000000ffffffff);
+        break;
+
       case AlphaISA::IPR_VA:
         // SFX: unlocks interrupt status registers
         retval = ipr[idx];

diff --git a/arch/alpha/isa_desc b/arch/alpha/isa_desc
index c4d367211e2a27fd47c04b4383cdf46b813c9fca..0cfe5b4525da299d4ae3486d790fad8ea99902ab 100644 (file)
--- a/arch/alpha/isa_desc
+++ b/arch/alpha/isa_desc
@@ -2390,8 +2390,7 @@ decode OPCODE default Unknown::unknown() {
        format BasicOperate {
            0xc000: rpcc({{
 #ifdef FULL_SYSTEM
-               uint64_t cc = xc->readIpr(AlphaISA::IPR_CC, fault);
-               Ra = (cc<63:32> | curTick<31:0>);
+               Ra = xc->readIpr(AlphaISA::IPR_CC, fault);
 #else
                Ra = curTick;
 #endif