prog->optLevel = info->optLevel;
switch (info->bin.sourceRep) {
- case NV50_PROGRAM_IR_TGSI:
+ case PIPE_SHADER_IR_TGSI:
ret = prog->makeFromTGSI(info) ? 0 : -2;
break;
default:
ubyte si; /* TGSI semantic index */
};
-#define NV50_PROGRAM_IR_TGSI 0
-#define NV50_PROGRAM_IR_SM4 1
-#define NV50_PROGRAM_IR_GLSL 2
-#define NV50_PROGRAM_IR_LLVM 3
-
#ifdef DEBUG
# define NV50_IR_DEBUG_BASIC (1 << 0)
# define NV50_IR_DEBUG_VERBOSE (2 << 0)
uint32_t *code;
uint32_t codeSize;
uint32_t instructions;
- uint8_t sourceRep; /* NV50_PROGRAM_IR */
+ uint8_t sourceRep; /* PIPE_SHADER_IR_* */
const void *source;
void *relocData;
void *fixupData;
info.type = type;
info.target = chipset;
- info.bin.sourceRep = NV50_PROGRAM_IR_TGSI;
+ info.bin.sourceRep = PIPE_SHADER_IR_TGSI;
info.bin.source = tokens;
info.io.auxCBSlot = 15;
* OTHER DEALINGS IN THE SOFTWARE.
*/
+#include "pipe/p_defines.h"
+
#include "nv50/nv50_program.h"
#include "nv50/nv50_context.h"
info->type = prog->type;
info->target = chipset;
- info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
+ info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
info->bin.source = (void *)prog->pipe.tokens;
info->io.auxCBSlot = 15;
info->type = prog->type;
info->target = chipset;
- info->bin.sourceRep = NV50_PROGRAM_IR_TGSI;
+ info->bin.sourceRep = PIPE_SHADER_IR_TGSI;
info->bin.source = (void *)prog->pipe.tokens;
#ifdef DEBUG