correct link

diff --git a/simple_v_extension/abridged_spec.mdwn b/simple_v_extension/abridged_spec.mdwn
index 8bf2ff7d9a1f6ab63da39017778241102731865a..9cf284f448cd59f816263474a86433c6754d36d3 100644 (file)
--- a/simple_v_extension/abridged_spec.mdwn
+++ b/simple_v_extension/abridged_spec.mdwn
@@ -261,7 +261,7 @@ of the RISC-V Spec.  It permits an optional VL/MVL/SUBVL block, up to 4
 and the rest of the instruction may be either standard RV opcodes or the
 SVPrefix opcodes ([[sv_prefix_proposal]])
 
-[[!inline raw="yes" pages="simple_v_extension/vblock_table_format" ]]
+[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]]
 
 For full details see ancillary resource: [[vblock_format]]
 

diff --git a/simple_v_extension/vblock_format.mdwn b/simple_v_extension/vblock_format.mdwn
index bf39c4d2c74daa0a05b88d9dd710b985ec9de4cf..d442ceaa7cca199c31e6e13f0f0f838296fc6387 100644 (file)
--- a/simple_v_extension/vblock_format.mdwn
+++ b/simple_v_extension/vblock_format.mdwn
@@ -23,7 +23,7 @@ The format is:
 Thus, the variable-length format from Section 1.5 of the RISC-V ISA is used
 as follows:
 
-[[!inline raw="yes" pages="simple_v_extension/vblock_table_format" ]]
+[[!inline raw="yes" pages="simple_v_extension/vblock_format_table" ]]
 
 Note: this format is very similar to that used in [[sv_prefix_proposal]]