Make the inferior's gdbarch field private, and add getters and setters.
This helped me by allowing putting breakpoints on set_arch to know when
the inferior's arch was set. A subsequent patch in this series also
adds more things in set_arch.
Change-Id: I0005bd1ef4cd6b612af501201cec44e457998eec
Reviewed-By: John Baldwin <jhb@FreeBSD.org>
Approved-By: Andrew Burgess <aburgess@redhat.com>
/* If this is a 32-bit architecture, then this is ARM, not AArch64.
There's no SVE vectors here, so just return the inferior
architecture. */
- if (gdbarch_bfd_arch_info (inf->gdbarch)->bits_per_word == 32)
- return inf->gdbarch;
+ if (gdbarch_bfd_arch_info (inf->arch ())->bits_per_word == 32)
+ return inf->arch ();
/* Only return the inferior's gdbarch if both vq and svq match the ones in
the tdep. */
aarch64_gdbarch_tdep *tdep
- = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->gdbarch);
+ = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->arch ());
uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
uint64_t svq = aarch64_za_get_svq (ptid.lwp ());
if (vq == tdep->vq && svq == tdep->sme_svq)
- return inf->gdbarch;
+ return inf->arch ();
/* We reach here if any vector length for the thread is different from its
value at process start. Lookup gdbarch via info (potentially creating a
new one) by using a target description that corresponds to the new vq/svq
value and the current architecture features. */
- const struct target_desc *tdesc = gdbarch_target_desc (inf->gdbarch);
+ const struct target_desc *tdesc = gdbarch_target_desc (inf->arch ());
aarch64_features features = aarch64_features_from_target_desc (tdesc);
features.vq = vq;
features.svq = svq;
if (it == info->breakpoint_map.end ())
error (_("Could not find breakpoint_id for breakpoint at %s"),
- paddress (inf->gdbarch, bs->bp_location_at->address));
+ paddress (inf->arch (), bs->bp_location_at->address));
amd_dbgapi_breakpoint_id_t breakpoint_id { it->first };
amd_dbgapi_breakpoint_action_t action;
if (status != AMD_DBGAPI_STATUS_SUCCESS)
error (_("amd_dbgapi_report_breakpoint_hit failed for breakpoint %ld "
"at %s (%s)"),
- breakpoint_id.handle, paddress (inf->gdbarch, bs->bp_location_at->address),
+ breakpoint_id.handle, paddress (inf->arch (), bs->bp_location_at->address),
get_status_string (status));
if (action == AMD_DBGAPI_BREAKPOINT_ACTION_RESUME)
ps_get_thread_area (struct ps_prochandle *ph,
lwpid_t lwpid, int idx, void **base)
{
- if (gdbarch_bfd_arch_info (ph->thread->inf->gdbarch)->bits_per_word == 32)
+ if (gdbarch_bfd_arch_info (ph->thread->inf->arch ())->bits_per_word == 32)
{
unsigned int base_addr;
ps_err_e result;
{
gdb_assert (new_gdbarch != NULL);
gdb_assert (new_gdbarch->initialized_p);
- current_inferior ()->gdbarch = new_gdbarch;
+ current_inferior ()->set_arch (new_gdbarch);
gdb::observers::architecture_changed.notify (new_gdbarch);
registers_changed ();
}
struct gdbarch *
target_gdbarch (void)
{
- return current_inferior ()->gdbarch;
+ return current_inferior ()->arch ();
}
void _initialize_gdbarch_utils ();
const gdb::optional<gdb::byte_vector> &auxv = target_read_auxv ();
return arm_fbsd_read_description_auxv (auxv,
current_inferior ()->top_target (),
- current_inferior ()->gdbarch,
+ current_inferior ()->arch (),
tls);
}
return -1;
return target_auxv_search (*auxv, current_inferior ()->top_target (),
- current_inferior ()->gdbarch, match, valp);
+ current_inferior ()->arch (), match, valp);
}
/* Print the description of a single AUXV entry on the specified file. */
size_t len = auxv->size ();
while (parse_auxv (current_inferior ()->top_target (),
- current_inferior ()->gdbarch,
+ current_inferior ()->arch (),
&ptr, data + len, &type, &val) > 0)
{
gdbarch_print_auxv_entry (gdbarch, file, type, val);
/* Setup the inferior's initial arch, based on information obtained
from the global "set ..." options. */
gdbarch_info info;
- inf->gdbarch = gdbarch_find_by_info (info);
+ inf->set_arch (gdbarch_find_by_info (info));
/* The "set ..." options reject invalid settings, so we should
always have a valid arch by now. */
- gdb_assert (inf->gdbarch != NULL);
+ gdb_assert (inf->arch () != nullptr);
return inf;
}
inf = add_inferior (0);
inf->pspace = pspace;
inf->aspace = pspace->aspace;
- inf->gdbarch = orginf->gdbarch;
+ inf->set_arch (orginf->arch ());
switch_to_inferior_and_push_target (inf, no_connection, orginf);
return m_cwd;
}
+ /* Set this inferior's arch. */
+ void set_arch (gdbarch *arch)
+ { m_gdbarch = arch; }
+
+ /* Get this inferior's arch. */
+ gdbarch *arch ()
+ { return m_gdbarch; }
+
/* Convenient handle (GDB inferior id). Unique across all
inferiors. */
int num = 0;
user supplied description's filename, if any; etc.). */
target_desc_info tdesc_info;
- /* The architecture associated with the inferior through the
- connection to the target.
-
- The architecture vector provides some information that is really
- a property of the inferior, accessed through a particular target:
- ptrace operations; the layout of certain RSP packets; the
- solib_ops vector; etc. To differentiate architecture accesses to
- per-inferior/target properties from
- per-thread/per-frame/per-objfile properties, accesses to
- per-inferior/target properties should be made through
- this gdbarch. */
- struct gdbarch *gdbarch = NULL;
-
/* Data related to displaced stepping. */
displaced_step_inferior_state displaced_step_state;
/* The current working directory that will be used when starting
this inferior. */
std::string m_cwd;
+
+ /* The architecture associated with the inferior through the
+ connection to the target.
+
+ The architecture vector provides some information that is really
+ a property of the inferior, accessed through a particular target:
+ ptrace operations; the layout of certain RSP packets; the
+ solib_ops vector; etc. To differentiate architecture accesses to
+ per-inferior/target properties from
+ per-thread/per-frame/per-objfile properties, accesses to
+ per-inferior/target properties should be made through
+ this gdbarch. */
+ gdbarch *m_gdbarch = nullptr;
};
/* Add an inferior to the inferior list, print a message that a new
child_inf->attach_flag = parent_inf->attach_flag;
copy_terminal_info (child_inf, parent_inf);
- child_inf->gdbarch = parent_inf->gdbarch;
+ child_inf->set_arch (parent_inf->arch ());
child_inf->tdesc_info = parent_inf->tdesc_info;
child_inf->symfile_flags = SYMFILE_NO_READ;
child_inf->attach_flag = parent_inf->attach_flag;
copy_terminal_info (child_inf, parent_inf);
- child_inf->gdbarch = parent_inf->gdbarch;
+ child_inf->set_arch (parent_inf->arch ());
child_inf->tdesc_info = parent_inf->tdesc_info;
if (has_vforked)
}
else
{
- struct gdbarch *gdbarch = current_inferior ()->gdbarch;
+ struct gdbarch *gdbarch = current_inferior ()->arch ();
if (gdbarch_gdb_signal_to_target_p (gdbarch))
{
static void
infrun_thread_ptid_changed ()
{
- gdbarch *arch = current_inferior ()->gdbarch;
+ gdbarch *arch = current_inferior ()->arch ();
/* The thread which inferior_ptid represents changes ptid. */
{
struct jit_descriptor descriptor;
struct jit_code_entry cur_entry;
CORE_ADDR cur_entry_addr;
- struct gdbarch *gdbarch = inf->gdbarch;
+ struct gdbarch *gdbarch = inf->arch ();
program_space *pspace = inf->pspace;
jit_debug_printf ("called");
/* Figure out the location of the buffers. They are contiguous, starting
at DISP_STEP_BUF_ADDR. They are all of size BUF_LEN. */
CORE_ADDR disp_step_buf_addr
- = linux_displaced_step_location (thread->inf->gdbarch);
+ = linux_displaced_step_location (thread->inf->arch ());
int buf_len = gdbarch_displaced_step_buffer_length (arch);
linux_gdbarch_data *gdbarch_data = get_linux_gdbarch_data (arch);
{
return linux_get_hwcap (target_read_auxv (),
current_inferior ()->top_target (),
- current_inferior ()->gdbarch);
+ current_inferior ()->arch ());
}
/* See linux-tdep.h. */
{
return linux_get_hwcap2 (target_read_auxv (),
current_inferior ()->top_target (),
- current_inferior ()->gdbarch);
+ current_inferior ()->arch ());
}
/* Display whether the gcore command is using the
{
/* Figure out where the displaced step buffer is. */
CORE_ADDR disp_step_buf_addr
- = linux_displaced_step_location (thread->inf->gdbarch);
+ = linux_displaced_step_location (thread->inf->arch ());
per_inferior->disp_step_buf.emplace (disp_step_buf_addr);
}
inferior *inf = ph->thread->inf;
return get_thread_arch_regcache (inf->process_target (),
ptid_t (inf->pid, lwpid),
- inf->gdbarch);
+ inf->arch ());
}
/* Get the general registers of LWP LWPID within the target process PH
{
inferior *inf = find_inferior_ptid (this, ptid);
gdb_assert (inf != NULL);
- return inf->gdbarch;
+ return inf->arch ();
}
bool
INFPY_REQUIRE_VALID (inf);
- return gdbarch_to_arch_object (inf->inferior->gdbarch);
+ return gdbarch_to_arch_object (inf->inferior->arch ());
}
/* Implement repr() for gdb.Inferior. */
/* Grab both of these from the current inferior, and its associated
default architecture. */
pspace = current_inferior ()->pspace;
- gdbarch = current_inferior ()->gdbarch;
+ gdbarch = current_inferior ()->arch ();
}
else if (arch_obj == nullptr || pspace_obj == nullptr)
{
/* We currently only test with a single gdbarch. Any gdbarch will do, so use
the current inferior's gdbarch. Also use the current inferior's address
space. */
- gdbarch *arch = inf_for_target_calls->gdbarch;
+ gdbarch *arch = inf_for_target_calls->arch ();
address_space *aspace = inf_for_target_calls->aspace;
regcache *regcache = get_thread_arch_aspace_regcache (inf_for_target_calls,
ptid, arch, aspace);
{
regcache_test_data ()
/* The specific arch doesn't matter. */
- : test_ctx_1 (current_inferior ()->gdbarch),
- test_ctx_2 (current_inferior ()->gdbarch)
+ : test_ctx_1 (current_inferior ()->arch ()),
+ test_ctx_2 (current_inferior ()->arch ())
{
/* Ensure the regcaches container is empty at the start. */
registers_changed ();
registers_changed ();
/* Any arch will do. */
- gdbarch *arch = current_inferior ()->gdbarch;
+ gdbarch *arch = current_inferior ()->arch ();
/* Prepare two targets with one thread each, with the same ptid. */
scoped_mock_context<test_target_ops> target1 (arch);
sr->ptid = tp->ptid;
sr->rs = rs;
sr->ws.set_stopped (GDB_SIGNAL_0);
- sr->arch = tp->inf->gdbarch;
+ sr->arch = tp->inf->arch ();
sr->stop_reason = TARGET_STOPPED_BY_NO_REASON;
sr->watch_data_address = 0;
sr->core = 0;
continue;
}
- event->arch = inf->gdbarch;
+ event->arch = inf->arch ();
rsa = event->rs->get_remote_arch_state (event->arch);
}
{
/* Figure out where the displaced step buffer is. */
CORE_ADDR disp_step_buf_addr
- = displaced_step_at_entry_point (thread->inf->gdbarch);
+ = displaced_step_at_entry_point (thread->inf->arch ());
per_inferior->disp_step_buf.emplace (disp_step_buf_addr);
}
mock_inferior.thread_list.push_back (mock_thread);
mock_inferior.ptid_thread_map[mock_ptid] = &mock_thread;
- mock_inferior.gdbarch = gdbarch;
+ mock_inferior.set_arch (gdbarch);
mock_inferior.aspace = mock_pspace.aspace;
mock_inferior.pspace = &mock_pspace;
rocm_solib_ops.handle_event = rocm_solib_handle_event;
/* Engage the ROCm so_ops. */
- set_gdbarch_so_ops (current_inferior ()->gdbarch, &rocm_solib_ops);
+ set_gdbarch_so_ops (current_inferior ()->arch (), &rocm_solib_ops);
}
}
{
struct mem_range vsyscall_range;
- if (gdbarch_vsyscall_range (inf->gdbarch, &vsyscall_range))
+ if (gdbarch_vsyscall_range (inf->arch (), &vsyscall_range))
{
struct bfd *bfd;
{
if (current_inferior () != nullptr)
{
- struct gdbarch *gdbarch = current_inferior ()->gdbarch;
+ gdbarch *gdbarch = current_inferior ()->arch ();
/* Check that tui_find_disassembly_address robustly handles the case of
being passed a PC for which gdb_print_insn throws a MEMORY_ERROR. */
test_user_created_frame ()
{
scoped_mock_context<test_target_ops> mock_context
- (current_inferior ()->gdbarch);
+ (current_inferior ()->arch ());
frame_info_ptr frame = create_new_frame (0x1234, 0x5678);
validate_user_created_frame (get_frame_id (frame));
static void
test_value_copy ()
{
- type *type = builtin_type (current_inferior ()->gdbarch)->builtin_int;
+ type *type = builtin_type (current_inferior ()->arch ())->builtin_int;
/* Verify that we can copy an entirely optimized out value, that may not have
its contents allocated. */