**SVP64 Vectorised**
-Vectorised Swizzle may be considered to be an extended static predicate
+Vectorised Swizzle may be considered to
+contain an extended static predicate
mask for subvectors (SUBVL=2/3/4). Due to the skipping caused by
the static predication capability, the destination
subvector length can be *different* from the source subvector
the Swizzle instruction requires that all Swizzled source elements be
copied into intermediary buffers (in-flight Reservation Stations,
pipeline registers) **before* being swapped and placed in
- destinations. Strict Program Order is required in full.
+ destinations. In-place (RT=RA) is required to work correctly.
+ Strict Program Order is required in full.
*Implementor's note: the cost of Vertical-First Mode in an Embedded design
of storing four 64-bit in-flight elements may be considered
the Swizzle Immediate. With the Swizzles marking what goes into
each destination position, the marker "0b001" may be used to indicate
the end. If no marker is present then the destination subvector length
-may be assimed to be 4.
-
-To determine the value to be copied from the source:
-
-```
-def get_src_from_dest(swiz, idx):
-
-```
+may be assumed to be 4.
**Effect of Saturation on Vectorised Swizzle**