targets/sim: fix

diff --git a/litex/boards/targets/sim.py b/litex/boards/targets/sim.py
index 04371fd9f70dc944b2bbf65922b0455c8d7416fb..a10479d2f33a48a4fb2bf97e5368bf25b41d6bca 100755 (executable)
--- a/litex/boards/targets/sim.py
+++ b/litex/boards/targets/sim.py
@@ -23,6 +23,11 @@ from liteeth.core.mac import LiteEthMAC
 from litex.build.sim.config import SimConfig
 
 class BaseSoC(SoCSDRAM):
+    interrupt_map = {
+        "uart": 2,
+    }
+    interrupt_map.update(SoCSDRAM.interrupt_map)
+
     def __init__(self, **kwargs):
         platform = sim.Platform()
         SoCSDRAM.__init__(self, platform,