S12Z opcodes: Fix bug disassembling certain shift instructions.

Shift and rotate instructions when the number of bit positions
was an immediate value greater than 1 were incorrectly disassembled.
This change fixes that problem and extends the test to check for
it.

gas/ChangeLog:

  testsuite/gas/s12z/shift.s: Add new test case.
  testsuite/gas/s12z/shift.d: Add expected result.

opcodes/ChangeLog:

  s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
  if the postbyte matches the appropriate pattern.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index c1d207df52fe73028476886830eaa7f12266aac7..1c99079dfe5681b7f47bfa6843433752a604f540 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-21 John Darrington <john@darrington.wattle.id.au>
+
+       * testsuite/gas/s12z/shift.s: Add new test case.
+       * testsuite/gas/s12z/shift.d: Add expected result.
+
 2018-11-21 John Darrington <john@darrington.wattle.id.au>
 
        * config/tc-s12z.c (opcodes): bhs, blo: New members.

diff --git a/gas/testsuite/gas/s12z/shift.d b/gas/testsuite/gas/s12z/shift.d
index c3244c4bbe9678d7cb41cbb97eac491b67b49cfe..f4747c9a991806132629a0e2bb0775dc7d607fbe 100644 (file)
--- a/gas/testsuite/gas/s12z/shift.d
+++ b/gas/testsuite/gas/s12z/shift.d
@@ -1,5 +1,5 @@
 #objdump: -d
-#name:    
+#name:    Tests for shift and rotate instructions
 #source:  shift.s
 
 
@@ -20,3 +20,5 @@ Disassembly of section .text:
   17:  10 3e 8e        lsr.p \(d6,x\), #2
   1a:  10 f4 bf        asl d7, #1
   1d:  10 bc bd        asr d1, #2
+  20:  16 de 78        asl d6, d6, #17
+  23:  16 d6 78        asl d6, d6, #16

diff --git a/gas/testsuite/gas/s12z/shift.s b/gas/testsuite/gas/s12z/shift.s
index cb41f3c030ffa3a5df70a52eb894a1dbf471f5ab..bf39580bb035e357a54cbd678f1baad6ae94afd1 100644 (file)
--- a/gas/testsuite/gas/s12z/shift.s
+++ b/gas/testsuite/gas/s12z/shift.s
@@ -9,3 +9,5 @@
        lsr.p (d6,x), #2
        asl   d7, #1
        asr   d1, #2
+       asl   d6, d6, #17
+       asl   d6, d6, #16

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index bfdca28ca5a1ce496d834df013ee7896bddbfcd8..d5c44b5087bf2034d8b3c99516faa76b98b4a154 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-11-21  John Darrington  <john@darrington.wattle.id.au>
+
+       * s12z-dis.c (print_insn_shift) [SB_REG_REG_N]: Enter special case
+       if the postbyte matches the appropriate pattern.
+
 2018-11-13  Francois H. Theron <francois.theron@netronome.com>
 
        * nfp-dis.c: Fix crc[] disassembly if operands are swapped.

diff --git a/opcodes/s12z-dis.c b/opcodes/s12z-dis.c
index ad39e052175f1038cd0ac3b1dc1c5d6f97900c25..719f172bcc3171a6a8accbd65551f2902a79c3b0 100644 (file)
--- a/opcodes/s12z-dis.c
+++ b/opcodes/s12z-dis.c
@@ -2363,25 +2363,31 @@ print_insn_shift (bfd_vma memaddr, struct disassemble_info* info, uint8_t byte)
       break;
 
     case SB_REG_REG_N:
-      if (sb & 0x08)
-       {
-         operand_separator (info);
-         if (byte & 0x10)
-           {
-             uint8_t xb;
-             read_memory (memaddr + 1, &xb, 1, info);
-             int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
-             (*info->fprintf_func) (info->stream, "#%d", shift);
-           }
-         else
-           {
-             (*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
-           }
-       }
-      else
-       {
-         opr_decode (memaddr + 1, info);
-       }
+      {
+        uint8_t xb;
+        read_memory (memaddr + 1, &xb, 1, info);
+        /* This case is slightly unusual.
+           If XB matches the binary pattern 0111XXXX, then instead of
+           interpreting this as a general OPR postbyte in the IMMe4 mode,
+           the XB byte is interpreted in s special way.  */
+        if ((xb & 0xF0) == 0x70)
+          {
+            operand_separator (info);
+            if (byte & 0x10)
+              {
+                int shift = ((sb & 0x08) >> 3) | ((xb & 0x0f) << 1);
+                (*info->fprintf_func) (info->stream, "#%d", shift);
+              }
+            else
+              {
+                (*info->fprintf_func) (info->stream, "%s:%d", __FILE__, __LINE__);
+              }
+          }
+        else
+          {
+            opr_decode (memaddr + 1, info);
+          }
+      }
       break;
     case SB_REG_OPR_OPR:
       {