Fix spacing in opt_share tests, change wording in opt_share help

diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index e9a2f05f9bd960c05468fbb038d3a7a7452fdb54..25b07cbbd2b9a1e875e6a14192d6b42e6fa9b8bd 100644 (file)
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -2,6 +2,7 @@
  *  yosys -- Yosys Open SYnthesis Suite
  *
  *  Copyright (C) 2012  Clifford Wolf <clifford@clifford.at>
+ *                2019  Bogdan Vukobratovic <bogdan.vukobratovic@gmail.com>
  *
  *  Permission to use, copy, modify, and/or distribute this software for any
  *  purpose with or without fee is hereby granted, provided that the above
@@ -308,17 +309,20 @@ void remove_multi_user_outbits(RTLIL::Module *module, dict<RTLIL::SigBit, RTLIL:
        }
 }
 
-struct OptRmdffPass : public Pass {
-       OptRmdffPass() : Pass("opt_share", "merge arithmetic operators that share an operand") {}
+struct OptSharePass : public Pass {
+       OptSharePass() : Pass("opt_share", "merge arithmetic operators that share an operand") {}
        void help() YS_OVERRIDE
        {
                //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
                log("\n");
                log("    opt_share [selection]\n");
                log("\n");
-               log("This pass identifies arithmetic operators that share an operand and whose\n");
-               log("results are used in mutually exclusive cases controlled by a multiplexer,\n");
-               log("and merges them together by multiplexing the other operands.\n");
+
+               log("This pass identifies mutually exclusive $alu arithmetic cells that:\n");
+               log("    (a) share an input operand\n");
+               log("    (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell allowing\n");
+               log("        the $alu cell to be merged and the multiplexer to be moved from\n");
+               log("        multiplexing its output to multiplexing the non-shared input operands.\n");
                log("\n");
        }
        void execute(std::vector<std::string>, RTLIL::Design *design) YS_OVERRIDE
@@ -454,6 +458,6 @@ struct OptRmdffPass : public Pass {
                }
        }
 
-} OptRmdffPass;
+} OptSharePass;
 
 PRIVATE_NAMESPACE_END

diff --git a/tests/opt/opt_share_add_sub.v b/tests/opt/opt_share_add_sub.v
index 30e093a39cc456cf984bf8f939663ca6358ddb3b..1c2665cf04804d29ef126902d32d216562eab569 100644 (file)
--- a/tests/opt/opt_share_add_sub.v
+++ b/tests/opt/opt_share_add_sub.v
@@ -1,10 +1,10 @@
 module opt_share_test(
-               input [15:0]  a,
-               input [15:0]  b,
-               input                            sel,
-               output [15:0] res,
-               );
+       input [15:0]    a,
+       input [15:0]    b,
+       input                           sel,
+       output [15:0] res,
+       );
 
-  assign res = {sel ? a + b : a - b};
+       assign res = {sel ? a + b : a - b};
 
 endmodule

diff --git a/tests/opt/opt_share_cat.v b/tests/opt/opt_share_cat.v
index 605dcfe59469bb4503518154eb702f7082f45e1d..7b6f626b97d0e09ff780032a37f903f3188192cb 100644 (file)
--- a/tests/opt/opt_share_cat.v
+++ b/tests/opt/opt_share_cat.v
@@ -1,15 +1,15 @@
 module opt_share_test(
-               input [15:0]  a,
-               input [15:0]  b,
-               input [15:0]  c,
-               input [15:0]  d,
-               input                            sel,
-               output [63:0] res,
-               );
+       input [15:0]    a,
+       input [15:0]    b,
+       input [15:0]    c,
+       input [15:0]    d,
+       input                           sel,
+       output [63:0] res,
+       );
 
-  reg [31: 0]                                                   cat1 = {a+b, c+d};
-  reg [31: 0]                                                   cat2 = {a-b, c-d};
+       reg [31: 0]     cat1 = {a+b, c+d};
+       reg [31: 0]     cat2 = {a-b, c-d};
 
-  assign res = {b, sel ? cat1 : cat2, a};
+       assign res = {b, sel ? cat1 : cat2, a};
 
 endmodule

diff --git a/tests/opt/opt_share_cat_multiuser.v b/tests/opt/opt_share_cat_multiuser.v
index 9ac0ceec82981b24c314c26a20fb5dab4486d0aa..f77f912e9cdc35aa3a7b03b6e50ed6c5149bea23 100644 (file)
--- a/tests/opt/opt_share_cat_multiuser.v
+++ b/tests/opt/opt_share_cat_multiuser.v
@@ -1,22 +1,22 @@
 module opt_share_test(
-               input [15:0]             a,
-               input [15:0]             b,
-               input [15:0]             c,
-               input [15:0]             d,
-               input                                            sel,
-               output reg [47:0] res,
-               );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [15:0]                    d,
+       input                                           sel,
+       output reg [47:0] res,
+       );
 
-  wire [15:0]                                                                   add_res = a+b;
-  wire [15:0]                                                                   sub_res = a-b;
-  wire [31: 0]                                                                          cat1 = {add_res, c+d};
-  wire [31: 0]                                                                          cat2 = {sub_res, c-d};
+       wire [15:0]                     add_res = a+b;
+       wire [15:0]                     sub_res = a-b;
+       wire [31: 0]                    cat1 = {add_res, c+d};
+       wire [31: 0]                    cat2 = {sub_res, c-d};
 
-  always @* begin
-    case(sel)
-      0: res = {cat1, add_res};
-      1: res = {cat2, add_res};
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = {cat1, add_res};
+                       1: res = {cat2, add_res};
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_diff_port_widths.v b/tests/opt/opt_share_diff_port_widths.v
index 5e2971e307730d54806d443e0a413a42ced9bf92..e57ab7a8353f58d1859c8fd586d48e3811575d12 100644 (file)
--- a/tests/opt/opt_share_diff_port_widths.v
+++ b/tests/opt/opt_share_diff_port_widths.v
@@ -1,21 +1,21 @@
 module opt_share_test(
-               input [15:0]             a,
-               input [15:0]             b,
-                                                        input [15:0]            c,
-                                                        input [1:0]                     sel,
-                                                        output reg [15:0] res
-               );
+       input [15:0]                     a,
+       input [15:0]                     b,
+       input [15:0]                     c,
+       input [1:0]                      sel,
+       output reg [15:0] res
+       );
 
-  wire [15:0]                                                   add0_res = a+b;
-  wire [15:0]                                                   add1_res = a+c;
+       wire [15:0]                     add0_res = a+b;
+       wire [15:0]                     add1_res = a+c;
 
-  always @* begin
-    case(sel)
-      0: res = add0_res[10:0];
-      1: res = add1_res[10:0];
-      2: res = a - b;
-      default: res = 32'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = add0_res[10:0];
+                       1: res = add1_res[10:0];
+                       2: res = a - b;
+                       default: res = 32'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_extend.v b/tests/opt/opt_share_extend.v
index 5ed6bde6f671e7a6067510510537773accd2a150..60ce1a2f39a9bfa96bb945fbbea1e78108ea8768 100644 (file)
--- a/tests/opt/opt_share_extend.v
+++ b/tests/opt/opt_share_extend.v
@@ -1,19 +1,18 @@
 module opt_share_test(
-                                                                                       input signed [7:0]                       a,
-                                                                                       input signed [10:0]              b,
-                                                                                       input signed [15:0]              c,
-                                                                                       input [1:0]                                              sel,
-                                                                                       output reg signed [15:0] res
-                                                                                       );
+       input signed [7:0]                       a,
+       input signed [10:0]                      b,
+       input signed [15:0]                      c,
+       input [1:0]                                                      sel,
+       output reg signed [15:0] res
+       );
 
-
-  always @* begin
-    case(sel)
-      0: res = a + b;
-      1: res = a - b;
-      2: res = a + c;
-      default: res = 16'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = a + b;
+                       1: res = a - b;
+                       2: res = a + c;
+                       default: res = 16'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_large_pmux_cat.v b/tests/opt/opt_share_large_pmux_cat.v
index 6208c796bedff6deb0f78631373913f8c56bc4b3..0667e60802656ab8556d929b794057f40926692f 100644 (file)
--- a/tests/opt/opt_share_large_pmux_cat.v
+++ b/tests/opt/opt_share_large_pmux_cat.v
@@ -1,22 +1,21 @@
 module opt_share_test(
-                                                                                       input [15:0]                    a,
-                                                                                       input [15:0]                    b,
-                                                                                       input [15:0]                    c,
-                                                                                       input [2:0]                     sel,
-                                                                                       output reg [31:0] res
-                                                                                       );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [2:0]                             sel,
+       output reg [31:0] res
+       );
 
-
-  always @* begin
-    case(sel)
-      0: res = {a + b, a};
-      1: res = {a - b, b};
-      2: res = {a + c, c};
-      3: res = {a - c, a};
-      4: res = {b, b};
-      5: res = {c, c};
-      default: res = 32'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = {a + b, a};
+                       1: res = {a - b, b};
+                       2: res = {a + c, c};
+                       3: res = {a - c, a};
+                       4: res = {b, b};
+                       5: res = {c, c};
+                       default: res = 32'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_large_pmux_cat_multipart.v b/tests/opt/opt_share_large_pmux_cat_multipart.v
index f97971bf67c8dc2ed8f8e92d4b1e3cbf0f7e3cd5..f26505d3a0f94e5034c159212280647d22809034 100644 (file)
--- a/tests/opt/opt_share_large_pmux_cat_multipart.v
+++ b/tests/opt/opt_share_large_pmux_cat_multipart.v
@@ -1,25 +1,25 @@
 module opt_share_test(
-                                                                                       input [15:0]                    a,
-                                                                                       input [15:0]                    b,
-                                                                                       input [15:0]                    c,
-                                                                                       input [15:0]                    d,
-                                                                                       input [2:0]                     sel,
-                                                                                       output reg [31:0] res
-                                                                                       );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [15:0]                    d,
+       input [2:0]                             sel,
+       output reg [31:0] res
+       );
 
-  wire [15:0]                                                                                                  add0_res = a+d;
+       wire [15:0]                     add0_res = a+d;
 
-  always @* begin
-    case(sel)
-      0: res = {add0_res, a};
-      1: res = {a - b, add0_res[7], 15'b0};
-      2: res = {b-a, b};
-      3: res = {d, b - c};
-      4: res = {d, b - a};
-      5: res = {c, d};
-      6: res = {a - c, b-d};
-      default: res = 32'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = {add0_res, a};
+                       1: res = {a - b, add0_res[7], 15'b0};
+                       2: res = {b-a, b};
+                       3: res = {d, b - c};
+                       4: res = {d, b - a};
+                       5: res = {c, d};
+                       6: res = {a - c, b-d};
+                       default: res = 32'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_large_pmux_multipart.v b/tests/opt/opt_share_large_pmux_multipart.v
index e7ba318efb2181f49dc8e11b35ec295fedcfc1cb..1c460292f043241a941c912dfe91de93f7d57357 100644 (file)
--- a/tests/opt/opt_share_large_pmux_multipart.v
+++ b/tests/opt/opt_share_large_pmux_multipart.v
@@ -1,24 +1,23 @@
 module opt_share_test(
-                                                                                       input [15:0]                    a,
-                                                                                       input [15:0]                    b,
-                                                                                       input [15:0]                    c,
-                                                                                       input [15:0]                    d,
-                                                                                       input [2:0]                     sel,
-                                                                                       output reg [15:0] res
-                                                                                       );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [15:0]                    d,
+       input [2:0]                             sel,
+       output reg [15:0] res
+       );
 
-
-  always @* begin
-    case(sel)
-      0: res = a + d;
-      1: res = a - b;
-      2: res = b;
-      3: res = b - c;
-      4: res = b - a;
-      5: res = c;
-      6: res = a - c;
-      default: res = 16'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = a + d;
+                       1: res = a - b;
+                       2: res = b;
+                       3: res = b - c;
+                       4: res = b - a;
+                       5: res = c;
+                       6: res = a - c;
+                       default: res = 16'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_large_pmux_part.v b/tests/opt/opt_share_large_pmux_part.v
index 138be0cd66e67f5400fcc39c96bc46b6225d83e3..f9dd174466c0daadd6911105cff9db2d4a4afe72 100644 (file)
--- a/tests/opt/opt_share_large_pmux_part.v
+++ b/tests/opt/opt_share_large_pmux_part.v
@@ -1,22 +1,21 @@
 module opt_share_test(
-                                                                                       input [15:0]                    a,
-                                                                                       input [15:0]                    b,
-                                                                                       input [15:0]                    c,
-                                                                                       input [2:0]                     sel,
-                                                                                       output reg [15:0] res
-                                                                                       );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [2:0]                             sel,
+       output reg [15:0] res
+       );
 
-
-  always @* begin
-    case(sel)
-      0: res = a + b;
-      1: res = a - b;
-      2: res = a + c;
-      3: res = a - c;
-      4: res = b;
-      5: res = c;
-      default: res = 16'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = a + b;
+                       1: res = a - b;
+                       2: res = a + c;
+                       3: res = a - c;
+                       4: res = b;
+                       5: res = c;
+                       default: res = 16'bx;
+               endcase
+       end
 
 endmodule

diff --git a/tests/opt/opt_share_mux_tree.v b/tests/opt/opt_share_mux_tree.v
index c90826204243f50f4873bf0030c6c2cfe4005085..4a26afb463019e25f9d450f3d709aecf5ecc885a 100644 (file)
--- a/tests/opt/opt_share_mux_tree.v
+++ b/tests/opt/opt_share_mux_tree.v
@@ -1,19 +1,18 @@
 module opt_share_test(
-               input [15:0]             a,
-               input [15:0]             b,
-               input [15:0]             c,
-               input [1:0]                      sel,
-               output reg [15:0] res
-               );
+       input [15:0]                    a,
+       input [15:0]                    b,
+       input [15:0]                    c,
+       input [1:0]                     sel,
+       output reg [15:0] res
+       );
 
-
-  always @* begin
-    case(sel)
-      0: res = a + b;
-      1: res = a - b;
-      2: res = a + c;
-      default: res = 16'bx;
-    endcase
-  end
+       always @* begin
+               case(sel)
+                       0: res = a + b;
+                       1: res = a - b;
+                       2: res = a + c;
+                       default: res = 16'bx;
+               endcase
+       end
 
 endmodule