+2019-05-22 Matthew Malcomson <matthew.malcomson@arm.com>
+
+ * common/config/aarch64/aarch64-common.c
+ (struct aarch64_option_extension, struct processor_name_to_arch,
+ struct arch_to_arch_name, aarch64_parse_extension, opt_ext_cmp,
+ aarch64_contains_opt,
+ aarch64_get_extension_string_for_isa_flags): Change type of
+ variables storing flags to uint64_t.
+ * config/aarch64/aarch64-option-extensions.def (sve2, sve2-sm4,
+ sve2-aes, sve2-sha3, bitperm): New optional SVE2 extension flags.
+ * config/aarch64/aarch64.c (struct processor,
+ aarch64_parse_arch, aarch64_parse_cpu, aarch64_validate_mcpu,
+ aarch64_validate_march, aarch64_override_options,
+ aarch64_option_print, aarch64_handle_attr_isa_flags,
+ aarch64_declare_function_name, aarch64_start_file): Make flag
+ variables uint64_t.
+ * config/aarch64/aarch64.h (AARCH64_FL_SVE2, AARCH64_FL_SVE2_AES,
+ AARCH64_FL_SVE2_SM4, AARCH64_FL_SVE2_SHA3,
+ AARCH64_FL_SVE2_BITPERM): New macro feature flags.
+ * config/aarch64/aarch64.opt (aarch64_isa_flags): Make uint64_t.
+ * config/aarch64/driver-aarch64.c
+ (struct aarch64_arch_extension, struct aarch64_core_data,
+ struct aarch64_arch_driver_info, host_detect_local_cpu): Make
+ flag variables uint64_t.
+ * doc/invoke.texi: Add documentation for new arguments.
+
2019-05-22 Richard Biener <rguenther@suse.de>
* alias.c (ao_ref_from_mem): Move stack-slot sharing
struct aarch64_option_extension
{
const char *const name;
- const unsigned long flag_canonical;
- const unsigned long flags_on;
- const unsigned long flags_off;
+ const uint64_t flag_canonical;
+ const uint64_t flags_on;
+ const uint64_t flags_off;
const bool is_synthetic;
};
{
const std::string processor_name;
const enum aarch64_arch arch;
- const unsigned long flags;
+ const uint64_t flags;
};
struct arch_to_arch_name
{
const enum aarch64_arch arch;
const std::string arch_name;
- const unsigned long flags;
+ const uint64_t flags;
};
/* Map processor names to the architecture revision they implement and
a copy of the string is created and stored to INVALID_EXTENSION. */
enum aarch64_parse_opt_result
-aarch64_parse_extension (const char *str, unsigned long *isa_flags,
+aarch64_parse_extension (const char *str, uint64_t *isa_flags,
std::string *invalid_extension)
{
/* The extension string is parsed left to right. */
turns on as a dependency. As an example +dotprod turns on FL_DOTPROD and
FL_SIMD. As such the set of bits represented by this option is
{FL_DOTPROD, FL_SIMD}. */
- unsigned long total_flags_a = opt_a->flag_canonical & opt_a->flags_on;
- unsigned long total_flags_b = opt_b->flag_canonical & opt_b->flags_on;
+ uint64_t total_flags_a = opt_a->flag_canonical & opt_a->flags_on;
+ uint64_t total_flags_b = opt_b->flag_canonical & opt_b->flags_on;
int popcnt_a = popcount_hwi ((HOST_WIDE_INT)total_flags_a);
int popcnt_b = popcount_hwi ((HOST_WIDE_INT)total_flags_b);
int order = popcnt_b - popcnt_a;
/* If they have the same amount of bits set, give it a more
deterministic ordering by using the value of the bits themselves. */
- if (order == 0)
- return total_flags_b - total_flags_a;
+ if (order != 0)
+ return order;
- return order;
+ if (total_flags_a != total_flags_b)
+ return total_flags_a < total_flags_b ? 1 : -1;
+
+ return 0;
}
/* Implement TARGET_OPTION_INIT_STRUCT. */
*/
static bool
-aarch64_contains_opt (unsigned long isa_flag_bits, opt_ext *opt)
+aarch64_contains_opt (uint64_t isa_flag_bits, opt_ext *opt)
{
- unsigned long flags_check
+ uint64_t flags_check
= opt->is_synthetic ? opt->flags_on : opt->flag_canonical;
return (isa_flag_bits & flags_check) == flags_check;
that all the "+" flags come before the "+no" flags. */
std::string
-aarch64_get_extension_string_for_isa_flags (unsigned long isa_flags,
- unsigned long default_arch_flags)
+aarch64_get_extension_string_for_isa_flags (uint64_t isa_flags,
+ uint64_t default_arch_flags)
{
const struct aarch64_option_extension *opt = NULL;
std::string outstr = "";
- unsigned long isa_flag_bits = isa_flags;
+ uint64_t isa_flag_bits = isa_flags;
/* Pass one: Minimize the search space by reducing the set of options
to the smallest set that still turns on the same features as before in
/* Enabling "fp" just enables "fp".
Disabling "fp" also disables "simd", "crypto", "fp16", "aes", "sha2",
- "sha3", sm3/sm4 and "sve". */
-AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE, false, "fp")
+ "sha3", sm3/sm4, "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
+ "bitperm". */
+AARCH64_OPT_EXTENSION("fp", AARCH64_FL_FP, 0, AARCH64_FL_SIMD | AARCH64_FL_CRYPTO | AARCH64_FL_F16 | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fp")
/* Enabling "simd" also enables "fp".
Disabling "simd" also disables "crypto", "dotprod", "aes", "sha2", "sha3",
- "sm3/sm4" and "sve". */
-AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE, false, "asimd")
+ "sm3/sm4", "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and "bitperm".
+ */
+AARCH64_OPT_EXTENSION("simd", AARCH64_FL_SIMD, AARCH64_FL_FP, AARCH64_FL_CRYPTO | AARCH64_FL_DOTPROD | AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "asimd")
/* Enabling "crypto" also enables "fp", "simd", "aes" and "sha2".
- Disabling "crypto" disables "crypto", "aes", "sha2", "sha3" and "sm3/sm4". */
-AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_AES | AARCH64_FL_SHA2, AARCH64_FL_AES | AARCH64_FL_SHA2 |AARCH64_FL_SHA3 | AARCH64_FL_SM4, true, "aes pmull sha1 sha2")
+ Disabling "crypto" disables "crypto", "aes", "sha2", "sha3" and "sm3/sm4",
+ "sve2-aes", "sve2-sha3", "sve2-sm4". */
+AARCH64_OPT_EXTENSION("crypto", AARCH64_FL_CRYPTO, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_AES | AARCH64_FL_SHA2, AARCH64_FL_AES | AARCH64_FL_SHA2 | AARCH64_FL_SHA3 | AARCH64_FL_SM4 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4, true, "aes pmull sha1 sha2")
/* Enabling or disabling "crc" only changes "crc". */
AARCH64_OPT_EXTENSION("crc", AARCH64_FL_CRC, 0, 0, false, "crc32")
AARCH64_OPT_EXTENSION("lse", AARCH64_FL_LSE, 0, 0, false, "atomics")
/* Enabling "fp16" also enables "fp".
- Disabling "fp16" disables "fp16", "fp16fml" and "sve". */
-AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE, false, "fphp asimdhp")
+ Disabling "fp16" disables "fp16", "fp16fml", "sve", "sve2", "sve2-aes",
+ "sve2-sha3", "sve2-sm4", and "bitperm". */
+AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, AARCH64_FL_F16FML | AARCH64_FL_SVE | AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "fphp asimdhp")
/* Enabling or disabling "rcpc" only changes "rcpc". */
AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, false, "lrcpc")
AARCH64_OPT_EXTENSION("dotprod", AARCH64_FL_DOTPROD, AARCH64_FL_SIMD, 0, false, "asimddp")
/* Enabling "aes" also enables "simd".
- Disabling "aes" just disables "aes". */
-AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, 0, false, "aes")
+ Disabling "aes" disables "aes" and "sve2-aes'. */
+AARCH64_OPT_EXTENSION("aes", AARCH64_FL_AES, AARCH64_FL_SIMD, AARCH64_FL_SVE2_AES, false, "aes")
/* Enabling "sha2" also enables "simd".
Disabling "sha2" just disables "sha2". */
AARCH64_OPT_EXTENSION("sha2", AARCH64_FL_SHA2, AARCH64_FL_SIMD, 0, false, "sha1 sha2")
/* Enabling "sha3" enables "simd" and "sha2".
- Disabling "sha3" just disables "sha3". */
-AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | AARCH64_FL_SHA2, 0, false, "sha3 sha512")
+ Disabling "sha3" disables "sha3" and "sve2-sha3". */
+AARCH64_OPT_EXTENSION("sha3", AARCH64_FL_SHA3, AARCH64_FL_SIMD | AARCH64_FL_SHA2, AARCH64_FL_SVE2_SHA3, false, "sha3 sha512")
/* Enabling "sm4" also enables "simd".
- Disabling "sm4" just disables "sm4". */
-AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, 0, false, "sm3 sm4")
+ Disabling "sm4" disables "sm4" and "sve2-sm4". */
+AARCH64_OPT_EXTENSION("sm4", AARCH64_FL_SM4, AARCH64_FL_SIMD, AARCH64_FL_SVE2_SM4, false, "sm3 sm4")
/* Enabling "fp16fml" also enables "fp" and "fp16".
Disabling "fp16fml" just disables "fp16fml". */
AARCH64_OPT_EXTENSION("fp16fml", AARCH64_FL_F16FML, AARCH64_FL_FP | AARCH64_FL_F16, 0, false, "asimdfml")
/* Enabling "sve" also enables "fp16", "fp" and "simd".
- Disabling "sve" just disables "sve". */
-AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, 0, false, "sve")
+ Disabling "sve" disables "sve", "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4"
+ and "bitperm". */
+AARCH64_OPT_EXTENSION("sve", AARCH64_FL_SVE, AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2 | AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "sve")
/* Enabling/Disabling "profile" does not enable/disable any other feature. */
AARCH64_OPT_EXTENSION("profile", AARCH64_FL_PROFILE, 0, 0, false, "")
/* Enabling/Disabling "predres" only changes "predres". */
AARCH64_OPT_EXTENSION("predres", AARCH64_FL_PREDRES, 0, 0, false, "")
+/* Enabling "sve2" also enables "sve", "fp16", "fp", and "simd".
+ Disabling "sve2" disables "sve2", "sve2-aes", "sve2-sha3", "sve2-sm4", and
+ "bitperm". */
+AARCH64_OPT_EXTENSION("sve2", AARCH64_FL_SVE2, AARCH64_FL_SVE | AARCH64_FL_FP | AARCH64_FL_SIMD | AARCH64_FL_F16, AARCH64_FL_SVE2_AES | AARCH64_FL_SVE2_SHA3 | AARCH64_FL_SVE2_SM4 | AARCH64_FL_SVE2_BITPERM, false, "")
+
+/* Enabling "sve2-sm4" also enables "sm4", "simd", "fp16", "fp", "sve", and
+ "sve2". Disabling "sve2-sm4" just disables "sve2-sm4". */
+AARCH64_OPT_EXTENSION("sve2-sm4", AARCH64_FL_SVE2_SM4, AARCH64_FL_SM4 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
+
+/* Enabling "sve2-aes" also enables "aes", "simd", "fp16", "fp", "sve", and
+ "sve2". Disabling "sve2-aes" just disables "sve2-aes". */
+AARCH64_OPT_EXTENSION("sve2-aes", AARCH64_FL_SVE2_AES, AARCH64_FL_AES | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
+
+/* Enabling "sve2-sha3" also enables "sha3", "simd", "fp16", "fp", "sve", and
+ "sve2". Disabling "sve2-sha3" just disables "sve2-sha3". */
+AARCH64_OPT_EXTENSION("sve2-sha3", AARCH64_FL_SVE2_SHA3, AARCH64_FL_SHA3 | AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
+
+/* Enabling "bitperm" also enables "simd", "fp16", "fp", "sve", and "sve2".
+ Disabling "bitperm" just disables "bitperm". */
+AARCH64_OPT_EXTENSION("bitperm", AARCH64_FL_SVE2_BITPERM, AARCH64_FL_SIMD | AARCH64_FL_F16 | AARCH64_FL_FP | AARCH64_FL_SVE | AARCH64_FL_SVE2, 0, false, "")
+
#undef AARCH64_OPT_EXTENSION
enum aarch64_processor aarch64_tune = cortexa53;
/* Mask to specify which instruction scheduling options should be used. */
-unsigned long aarch64_tune_flags = 0;
+uint64_t aarch64_tune_flags = 0;
/* Global flag for PC relative loads. */
bool aarch64_pcrelative_literal_loads;
enum aarch64_processor sched_core;
enum aarch64_arch arch;
unsigned architecture_version;
- const unsigned long flags;
+ const uint64_t flags;
const struct tune_params *const tune;
};
static enum aarch64_parse_opt_result
aarch64_parse_arch (const char *to_parse, const struct processor **res,
- unsigned long *isa_flags, std::string *invalid_extension)
+ uint64_t *isa_flags, std::string *invalid_extension)
{
const char *ext;
const struct processor *arch;
if (strlen (arch->name) == len
&& strncmp (arch->name, to_parse, len) == 0)
{
- unsigned long isa_temp = arch->flags;
+ uint64_t isa_temp = arch->flags;
if (ext != NULL)
{
static enum aarch64_parse_opt_result
aarch64_parse_cpu (const char *to_parse, const struct processor **res,
- unsigned long *isa_flags, std::string *invalid_extension)
+ uint64_t *isa_flags, std::string *invalid_extension)
{
const char *ext;
const struct processor *cpu;
{
if (strlen (cpu->name) == len && strncmp (cpu->name, to_parse, len) == 0)
{
- unsigned long isa_temp = cpu->flags;
+ uint64_t isa_temp = cpu->flags;
if (ext != NULL)
static bool
aarch64_validate_mcpu (const char *str, const struct processor **res,
- unsigned long *isa_flags)
+ uint64_t *isa_flags)
{
std::string invalid_extension;
enum aarch64_parse_opt_result parse_res
static bool
aarch64_validate_march (const char *str, const struct processor **res,
- unsigned long *isa_flags)
+ uint64_t *isa_flags)
{
std::string invalid_extension;
enum aarch64_parse_opt_result parse_res
static void
aarch64_override_options (void)
{
- unsigned long cpu_isa = 0;
- unsigned long arch_isa = 0;
+ uint64_t cpu_isa = 0;
+ uint64_t arch_isa = 0;
aarch64_isa_flags = 0;
bool valid_cpu = true;
{
const struct processor *cpu
= aarch64_get_tune_cpu (ptr->x_explicit_tune_core);
- unsigned long isa_flags = ptr->x_aarch64_isa_flags;
+ uint64_t isa_flags = ptr->x_aarch64_isa_flags;
const struct processor *arch = aarch64_get_arch (ptr->x_explicit_arch);
std::string extension
= aarch64_get_extension_string_for_isa_flags (isa_flags, arch->flags);
aarch64_handle_attr_isa_flags (char *str)
{
enum aarch64_parse_opt_result parse_res;
- unsigned long isa_flags = aarch64_isa_flags;
+ uint64_t isa_flags = aarch64_isa_flags;
/* We allow "+nothing" in the beginning to clear out all architectural
features if the user wants to handpick specific features. */
const struct processor *this_arch
= aarch64_get_arch (targ_options->x_explicit_arch);
- unsigned long isa_flags = targ_options->x_aarch64_isa_flags;
+ uint64_t isa_flags = targ_options->x_aarch64_isa_flags;
std::string extension
= aarch64_get_extension_string_for_isa_flags (isa_flags,
this_arch->flags);
const struct processor *default_arch
= aarch64_get_arch (default_options->x_explicit_arch);
- unsigned long default_isa_flags = default_options->x_aarch64_isa_flags;
+ uint64_t default_isa_flags = default_options->x_aarch64_isa_flags;
std::string extension
= aarch64_get_extension_string_for_isa_flags (default_isa_flags,
default_arch->flags);
/* Execution and Data Prediction Restriction instructions supported. */
#define AARCH64_FL_PREDRES (1 << 27)
+/* SVE2 instruction supported. */
+#define AARCH64_FL_SVE2 (1 << 28)
+#define AARCH64_FL_SVE2_AES (1 << 29)
+#define AARCH64_FL_SVE2_SM4 (1 << 30)
+#define AARCH64_FL_SVE2_SHA3 (1ULL << 31)
+#define AARCH64_FL_SVE2_BITPERM (1ULL << 32)
+
/* Has FP and SIMD. */
#define AARCH64_FL_FPSIMD (AARCH64_FL_FP | AARCH64_FL_SIMD)
const char *x_aarch64_override_tune_string
TargetVariable
-unsigned long aarch64_isa_flags = 0
+uint64_t aarch64_isa_flags = 0
TargetVariable
unsigned aarch64_enable_bti = 2
struct aarch64_arch_extension
{
const char *ext;
- unsigned int flag;
+ uint64_t flag;
const char *feat_string;
};
unsigned char implementer_id; /* Exactly 8 bits */
unsigned int part_no; /* 12 bits + 12 bits */
unsigned variant;
- const unsigned long flags;
+ const uint64_t flags;
};
#define AARCH64_BIG_LITTLE(BIG, LITTLE) \
{
const char* id;
const char* name;
- const unsigned long flags;
+ const uint64_t flags;
};
#define AARCH64_ARCH(NAME, CORE, ARCH_IDENT, ARCH_REV, FLAGS) \
unsigned int variants[2] = { ALL_VARIANTS, ALL_VARIANTS };
unsigned int n_variants = 0;
bool processed_exts = false;
- unsigned long extension_flags = 0;
- unsigned long default_flags = 0;
+ uint64_t extension_flags = 0;
+ uint64_t default_flags = 0;
gcc_assert (argc);
Enable the Armv8-a Execution and Data Prediction Restriction instructions.
This option is only to enable the extension at the assembler level and does
not affect code generation. This option is enabled by default for
+@item sve2
+Enable the Armv8-a Scalable Vector Extension 2. This also enables SVE
+instructions.
+@item bitperm
+Enable SVE2 bitperm instructions. This also enables SVE2 instructions.
+@item sve2-sm4
+Enable SVE2 sm4 instructions. This also enables SVE2 instructions.
+@item sve2-aes
+Enable SVE2 aes instructions. This also enables SVE2 instructions.
+@item sve2-sha3
+Enable SVE2 sha3 instructions. This also enables SVE2 instructions.
@option{-march=armv8.5-a}.
@end table
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