Revert "abc9 to write_xaiger -symbols, not -map"

This reverts commit 04429f8152ae64de050580ec20db60ac6dc1c0e1.

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 30cd688817ceaee68128c3bb6c166288b46f268b..d652ef05a349876476bc606cf2ba112de768f4e9 100644 (file)
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -407,7 +407,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
 
        handle_loops(design);
 
-    Pass::call(design, stringf("write_xaiger -O -symbols %s/input.xaig; ", tempdir_name.c_str()));
+    Pass::call(design, stringf("write_xaiger -O -map %s/input.symbols %s/input.xaig; ", tempdir_name.c_str(), tempdir_name.c_str()));
 
        // Now 'unexpose' those wires by undoing
        // the expose operation -- remove them from PO/PI
@@ -518,7 +518,8 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
                bool builtin_lib = liberty_file.empty();
                RTLIL::Design *mapped_design = new RTLIL::Design;
                //parse_blif(mapped_design, ifs, builtin_lib ? "\\DFF" : "\\_dff_", false, sop_mode);
-               AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", "", true /* wideports */);
+               buffer = stringf("%s/%s", tempdir_name.c_str(), "input.symbols");
+               AigerReader reader(mapped_design, ifs, "\\netlist", "\\clk", buffer, true /* wideports */);
                reader.parse_xaiger();
 
                ifs.close();