(no commit message)

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index 103a8c3b2e669a98f5eaccd1d9a3b787b6e2de7a..bbcc3ced986ea43bf4e2cc590286c4e9951f363b 100644 (file)
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -76,8 +76,9 @@ Advantages of these design principles:
 Comparative instruction count:
 
 * ARM NEON SIMD: around 2,000 instructions, prerequisite: ARM Scalar.
-* ARM SVE: around 4,000 instructions, prerequisite: NEON. 
-* ARM SVE2: around 1,000 instructions, prerequisite: SVE
+* ARM SVE: around 4,000 instructions, prerequisite: NEON and ARM Scalar 
+* ARM SVE2: around 1,000 instructions, prerequisite: SVE, NEON, and
+  ARM Scalar
 * Intel AVX-512: around 4,000 instructions, prerequisite AVX, AVX2,
   AVX-128 and AVX-256 which in turn critically rely on the rest of
   x86, for a grand total of well over 10,000 instructions.
@@ -203,7 +204,8 @@ Vector ISAs may be found at the [[sv/vector_isa_comparison]] page.
 Note: AVX-512 and SVE2 are *not Vector ISAs*, they are Predicated-SIMD.
 *Public discussions have taken place at Conferences attended by both Intel
 and ARM on adding a `setvl` instruction which would easily make both
-AVX-512 and SVE2 truly "Scalable".*
+AVX-512 and SVE2 truly "Scalable".*  [[sv/comparison_table]] in tabular
+form.
 
 # Major opcodes summary