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author
Korey Sewell
<ksewell@umich.edu>
Wed, 14 Nov 2007 20:33:43 +0000
(15:33 -0500)
committer
Korey Sewell
<ksewell@umich.edu>
Wed, 14 Nov 2007 20:33:43 +0000
(15:33 -0500)
--HG--
extra : convert_revision :
b3acde37bc11919700c257eae58ea9e0f66c9786
src/arch/mips/tlb.hh
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diff --git
a/src/arch/mips/tlb.hh
b/src/arch/mips/tlb.hh
index 5240eb2a9cabc2d03f241c7452075c58fc579fc0..0dfe3ecf1ca240e69299debc8a27d6135201d0e8 100644
(file)
--- a/
src/arch/mips/tlb.hh
+++ b/
src/arch/mips/tlb.hh
@@
-53,7
+53,6
@@
class ThreadContext;
namespace MipsISA {
// WARN: This particular TLB entry is not necessarily conformed to MIPS ISA
-// We just need this to make compiler happy. Use "PTE" type for real entry.
struct TlbEntry
{
Addr _pageStart;