vendor.xilinx_{7series,spartan6}: Support extra VHDL files.

diff --git a/nmigen/vendor/xilinx_7series.py b/nmigen/vendor/xilinx_7series.py
index 3c43b089ee11ed3c0fb663e96c29396d859ee2d3..7b06cdb9ec7f29bea027791e60f07e70f3b26873 100644 (file)
--- a/nmigen/vendor/xilinx_7series.py
+++ b/nmigen/vendor/xilinx_7series.py
@@ -55,7 +55,7 @@ class Xilinx7SeriesPlatform(TemplatedPlatform):
         "{{name}}.tcl": r"""
             # {{autogenerated}}
             create_project -force -name {{name}} -part {{platform.device}}{{platform.package}}-{{platform.speed}}
-            {% for file in platform.iter_extra_files(".v", ".sv") -%}
+            {% for file in platform.iter_extra_files(".v", ".sv", ".vhd", ".vhdl") -%}
                 add_files {{file}}
             {% endfor %}
             add_files {{name}}.v

diff --git a/nmigen/vendor/xilinx_spartan6.py b/nmigen/vendor/xilinx_spartan6.py
index 4a0d3a6e8c74d9959eaa1eaea20d0aa1eb2c615c..7ac360a46c84efedb037d3a188b6a7c6373da2e6 100644 (file)
--- a/nmigen/vendor/xilinx_spartan6.py
+++ b/nmigen/vendor/xilinx_spartan6.py
@@ -57,6 +57,9 @@ class XilinxSpartan6Platform(TemplatedPlatform):
         """,
         "{{name}}.prj": r"""
             # {{autogenerated}}
+            {% for file in platform.iter_extra_files(".vhd", ".vhdl") -%}
+                vhdl work {{file}}
+            {% endfor %}
             {% for file in platform.iter_extra_files(".v") -%}
                 verilog work {{file}}
             {% endfor %}