radeonsi: don't use pipe_constant_buffer for GS rings

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index a0780cd745728ac51806032d5e473acd7de235a7..fc535d01a8401e1456da1ee2c92d9ad4cf85eab5 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -732,7 +732,7 @@ static void si_set_constant_buffer(struct pipe_context *ctx, uint shader, uint s
 /* RING BUFFERS */
 
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
-                       struct pipe_constant_buffer *input,
+                       struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
                        unsigned element_size, unsigned index_stride)
@@ -749,10 +749,10 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
        assert(slot < buffers->num_buffers);
        pipe_resource_reference(&buffers->buffers[slot], NULL);
 
-       if (input && input->buffer) {
+       if (buffer) {
                uint64_t va;
 
-               va = r600_resource(input->buffer)->gpu_address;
+               va = r600_resource(buffer)->gpu_address;
 
                switch (element_size) {
                default:
@@ -807,9 +807,9 @@ void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
                          S_008F0C_INDEX_STRIDE(index_stride) |
                          S_008F0C_ADD_TID_ENABLE(add_tid);
 
-               pipe_resource_reference(&buffers->buffers[slot], input->buffer);
+               pipe_resource_reference(&buffers->buffers[slot], buffer);
                r600_context_bo_reloc(&sctx->b, &sctx->b.rings.gfx,
-                                     (struct r600_resource*)input->buffer,
+                                     (struct r600_resource*)buffer,
                                      buffers->shader_usage, buffers->priority);
                buffers->desc.enabled_mask |= 1 << slot;
        } else {

diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 4b223b48d36e32ec0cac36a63eeca9864400de4c..5f5404dd4cc232c0f810074238fe42f4a280ce76 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -154,8 +154,8 @@ struct si_context {
        struct si_pm4_state     *gs_rings;
        struct r600_atom        cache_flush;
        struct pipe_constant_buffer null_const_buf; /* used for set_constant_buffer(NULL) on CIK */
-       struct pipe_constant_buffer esgs_ring;
-       struct pipe_constant_buffer gsvs_ring;
+       struct pipe_resource    *esgs_ring;
+       struct pipe_resource    *gsvs_ring;
 
        /* SI state handling */
        union si_state  queued;

diff --git a/src/gallium/drivers/radeonsi/si_state.h b/src/gallium/drivers/radeonsi/si_state.h
index a5c6720746ad29b841d030cd467c1a63d3fac55d..d3a745a1048b22a0be45391393bc761a82b17148 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -234,7 +234,7 @@ void si_set_sampler_descriptors(struct si_context *sctx, unsigned shader,
                                unsigned start, unsigned count, void **states);
 void si_update_vertex_buffers(struct si_context *sctx);
 void si_set_ring_buffer(struct pipe_context *ctx, uint shader, uint slot,
-                       struct pipe_constant_buffer *input,
+                       struct pipe_resource *buffer,
                        unsigned stride, unsigned num_records,
                        bool add_tid, bool swizzle,
                        unsigned element_size, unsigned index_stride);

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c
index a9dedf9096f966121b698e62e89b736a452485c9..61951eeec9ec42d57f34c06e7eb9b861c7afddfb 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -550,42 +550,38 @@ bcolor:
 /* Initialize state related to ESGS / GSVS ring buffers */
 static void si_init_gs_rings(struct si_context *sctx)
 {
-       unsigned size = 128 * 1024;
+       unsigned esgs_ring_size = 128 * 1024;
+       unsigned gsvs_ring_size = 64 * 1024 * 1024;
 
        assert(!sctx->gs_rings);
        sctx->gs_rings = si_pm4_alloc_state(sctx);
 
-       sctx->esgs_ring.buffer =
-               pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
-                                  PIPE_USAGE_DEFAULT, size);
-       sctx->esgs_ring.buffer_size = size;
+       sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
+                                      PIPE_USAGE_DEFAULT, esgs_ring_size);
 
-       size = 64 * 1024 * 1024;
-       sctx->gsvs_ring.buffer =
-               pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
-                                  PIPE_USAGE_DEFAULT, size);
-       sctx->gsvs_ring.buffer_size = size;
+       sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
+                                            PIPE_USAGE_DEFAULT, gsvs_ring_size);
 
        if (sctx->b.chip_class >= CIK) {
                si_pm4_set_reg(sctx->gs_rings, R_030900_VGT_ESGS_RING_SIZE,
-                              sctx->esgs_ring.buffer_size / 256);
+                              esgs_ring_size / 256);
                si_pm4_set_reg(sctx->gs_rings, R_030904_VGT_GSVS_RING_SIZE,
-                              sctx->gsvs_ring.buffer_size / 256);
+                              gsvs_ring_size / 256);
        } else {
                si_pm4_set_reg(sctx->gs_rings, R_0088C8_VGT_ESGS_RING_SIZE,
-                              sctx->esgs_ring.buffer_size / 256);
+                              esgs_ring_size / 256);
                si_pm4_set_reg(sctx->gs_rings, R_0088CC_VGT_GSVS_RING_SIZE,
-                              sctx->gsvs_ring.buffer_size / 256);
+                              gsvs_ring_size / 256);
        }
 
        si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_ESGS,
-                          &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+                          sctx->esgs_ring, 0, esgs_ring_size,
                           true, true, 4, 64);
        si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_GEOMETRY, SI_RING_ESGS,
-                          &sctx->esgs_ring, 0, sctx->esgs_ring.buffer_size,
+                          sctx->esgs_ring, 0, esgs_ring_size,
                           false, false, 0, 0);
        si_set_ring_buffer(&sctx->b.b, PIPE_SHADER_VERTEX, SI_RING_GSVS,
-                          &sctx->gsvs_ring, 0, sctx->gsvs_ring.buffer_size,
+                          sctx->gsvs_ring, 0, gsvs_ring_size,
                           false, false, 0, 0);
 }
 
@@ -632,7 +628,7 @@ static void si_update_derived_state(struct si_context *sctx)
                si_pm4_bind_state(sctx, gs_rings, sctx->gs_rings);
 
                si_set_ring_buffer(ctx, PIPE_SHADER_GEOMETRY, SI_RING_GSVS,
-                                  &sctx->gsvs_ring,
+                                  sctx->gsvs_ring,
                                   sctx->gs_shader->current->gs_max_out_vertices *
                                   sctx->gs_shader->current->noutput * 16,
                                   64, true, true, 4, 16);