radeonsi/gfx9: make some PA & DB registers match the closed Vulkan driver

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

diff --git a/src/amd/common/gfx9d.h b/src/amd/common/gfx9d.h
index e295a1da820b8e0c7f881cc0e160f084e8f77ec9..787d0a94dfb5469c110a8d8a6afbbe68b7a6ee82 100644 (file)
--- a/src/amd/common/gfx9d.h
+++ b/src/amd/common/gfx9d.h
@@ -4074,6 +4074,10 @@
 #define   S_028060_PUNCHOUT_MODE(x)                                   (((unsigned)(x) & 0x03) << 0)
 #define   G_028060_PUNCHOUT_MODE(x)                                   (((x) >> 0) & 0x03)
 #define   C_028060_PUNCHOUT_MODE                                      0xFFFFFFFC
+#define     V_028060_AUTO                                              0
+#define     V_028060_FORCE_ON                                          1
+#define     V_028060_FORCE_OFF                                         2
+#define     V_028060_RESERVED                                          3
 #define   S_028060_POPS_DRAIN_PS_ON_OVERLAP(x)                        (((unsigned)(x) & 0x1) << 2)
 #define   G_028060_POPS_DRAIN_PS_ON_OVERLAP(x)                        (((x) >> 2) & 0x1)
 #define   C_028060_POPS_DRAIN_PS_ON_OVERLAP                           0xFFFFFFFB

diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index e967b4b493cb439e1c8f56be136f8f6e2e03d9f8..9d5804c380a5066aa6cef41f421517ba17e1c4f7 100644 (file)
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -4568,15 +4568,30 @@ static void si_init_config(struct si_context *sctx)
                      RADEON_PRIO_BORDER_COLORS);
 
        if (sctx->b.chip_class >= GFX9) {
-               si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL, 0);
+               unsigned num_se = sscreen->b.info.max_se;
+               unsigned pc_lines = 0;
+
+               switch (sctx->b.family) {
+               case CHIP_VEGA10:
+                       pc_lines = 4096;
+                       break;
+               default:
+                       assert(0);
+               }
+
+               si_pm4_set_reg(pm4, R_028060_DB_DFSM_CONTROL,
+                              S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
                si_pm4_set_reg(pm4, R_028064_DB_RENDER_FILTER, 0);
                /* TODO: We can use this to disable RBs for rendering to GART: */
                si_pm4_set_reg(pm4, R_02835C_PA_SC_TILE_STEERING_OVERRIDE, 0);
                si_pm4_set_reg(pm4, R_02883C_PA_SU_OVER_RASTERIZATION_CNTL, 0);
                /* TODO: Enable the binner: */
                si_pm4_set_reg(pm4, R_028C44_PA_SC_BINNER_CNTL_0,
-                              S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC));
-               si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1, 0);
+                              S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
+                              S_028C44_DISABLE_START_OF_PRIM(1));
+               si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
+                              S_028C48_MAX_ALLOC_COUNT(MIN2(128, pc_lines / (4 * num_se))) |
+                              S_028C48_MAX_PRIM_PER_BATCH(1023));
                si_pm4_set_reg(pm4, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
                               S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1));
                si_pm4_set_reg(pm4, R_030968_VGT_INSTANCE_BASE_ID, 0);